Karthik Ganesan

According to our database1, Karthik Ganesan authored at least 28 papers between 2007 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Article 
PhD thesis 
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Links

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Bibliography

2019
Boosting the Bounds of Symbolic QED for Effective Pre-Silicon Verification of Processor Cores.
CoRR, 2019

Unlocking the Power of Formal Hardware Verification with CoSA and Symbolic QED: Invited Paper.
Proceedings of the International Conference on Computer-Aided Design, 2019

The What's Next Intermittent Computing Architecture.
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019

Symbolic QED Pre-silicon Verification for Automotive Microcontroller Cores: Industrial Case Study.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Review of Methodologies for Pre- and Post-Silicon Analog Verification in Mixed-Signal SOCs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
The EH Model: Analytical Exploration of Energy-Harvesting Architectures.
Computer Architecture Letters, 2018

The EH Model: Early Design Space Exploration of Intermittent Processor Architectures.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

2017
Accelerating Java Streams With A Data AnalyticsHardware Accelerator.
Proceedings of the 8th ACM/SPEC on International Conference on Performance Engineering, 2017

Measuring the Power-Constrained Performance and Energy Gap between FPGAs and Processors (Abstract Only).
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

2016
TPAD: Hardware Trojan Prevention and Detection for Trusted Integrated Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

On the Total Power Capacity of Regular-LDPC Codes With Iterative Message-Passing Decoders.
IEEE Journal on Selected Areas in Communications, 2016

2015
Towards Approaching Total-Power-Capacity: Transmit and Decoding Power Minimization for LDPC Codes.
CoRR, 2015

QVZ: lossy compression of quality values.
Bioinformatics, 2015

i-MIRROR: A Software Managed Die-Stacked DRAM-Based Memory Subsystem.
Proceedings of the 27th International Symposium on Computer Architecture and High Performance Computing, 2015

2014
Automatic Generation of Miniaturized Synthetic Proxies for Target Applications to Efficiently Design Multicore Processors.
IEEE Trans. Computers, 2014

Scaling Java Virtual Machine on a many-core system.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

2012
Choosing "green" codes by simulation-based modeling of implementations.
Proceedings of the 2012 IEEE Global Communications Conference, 2012

How far are LDPC codes from fundamental limits on total power consumption?
Proceedings of the 50th Annual Allerton Conference on Communication, 2012

2011
The power cost of over-designing codes.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2011

MAximum Multicore POwer (MAMPO): an automatic multithreaded synthetic power virus generation framework for multicore systems.
Proceedings of the Conference on High Performance Computing Networking, 2011

"Green codes with short wires at the decoder: Fundamental limits and constructions".
Proceedings of the Information Theory and Applications Workshop, 2011

2010
Synthesizing memory-level parallelism aware miniature clones for SPEC CPU2006 and ImplantBench workloads.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2010

System-level max power (SYMPO): a systematic approach for escalating system-level power consumption using synthetic benchmarks.
Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010

2009
Generation, Validation and Analysis of SPEC CPU2006 Simulation Points Based on Branch, Memory and TLB Characteristics.
Proceedings of the Computer Performance Evaluation and Benchmarking, 2009

2008
Next-Generation Performance Counters: Towards Monitoring Over Thousand Concurrent Events.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2008

On the concept of simultaneous execution of multiple applications on hierarchically based cluster and the silicon operating system.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

A Performance Counter Based Workload Characterization on Blue Gene/P.
Proceedings of the 2008 International Conference on Parallel Processing, 2008

2007
Future generation supercomputers II: a paradigm for cluster architecture.
SIGARCH Computer Architecture News, 2007


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