Kazuo Murano

According to our database1, Kazuo Murano authored at least 12 papers between 1978 and 2000.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Awards

IEEE Fellow

IEEE Fellow 2002, "For contributions to the research and development of communications signal processing and DSP LSIs, and the standardization of ISDN user-network interface.".

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2000
The network paradigm of the 21st century and its key technologies.
IEEE Commun. Mag., 2000

1990
Echo cancellation and applications.
IEEE Commun. Mag., 1990

Technologies towards broadband ISDN.
IEEE Commun. Mag., 1990

1986
Implementation of a 32 Kbit/s ADPCM Codec Using a General-Purpose Digital Signal Processor.
IEEE J. Sel. Areas Commun., 1986

Phased Aligned Passive Bus (PAB) Scheme for ISDN User-Network Interface.
IEEE J. Sel. Areas Commun., 1986

A Processor VLSI for Multiplexing and Circuit Termination Functions - MUX Processor.
Proceedings of the IEEE International Conference on Communications: Integrating the World Through Communications, 1986

A 32kbps ADPCM with improvement in coding characteristics for 9600bps modem signal.
Proceedings of the IEEE International Conference on Acoustics, 1986

Frequency domain noise canceller: Frequency bin adaptive filtering (FBAF).
Proceedings of the IEEE International Conference on Acoustics, 1986

1985
A High Performance LSI Digital Signal Processor for Communication.
IEEE J. Sel. Areas Commun., 1985

1983
CMOS LSI DSP and its application to voice band signals.
Proceedings of the IEEE International Conference on Acoustics, 1983

1982
TDM-FDM Transmultiplexer Using a Digital Signal Processor.
IEEE Trans. Commun., 1982

1978
LSI Processor for Digital Signal Processing and Its Application to 4800 Bit/s Modem.
IEEE Trans. Commun., 1978


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