Kazuo Nishitani

According to our database, Kazuo Nishitani authored at least 4 papers between 1990 and 1999.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

1999

A 2.2-V operation, 2.4-GHz single-chip GaAs MMIC transceiver for wireless applications.

Kazuya Yamamoto, Takao Moriwaki, Takayuki Fujii, Jun Otsuji, Miyo Miyashita, Yukio Miyazaki, Kazuo Nishitani

IEEE J. Solid State Circuits, 1999

1998

Design and Experimental Results of a 2V-Operation Single-Chip GaAs T/R-MMIC Front-End for 1.9-GHz Personal Communications.

Kazuya Yamamoto, Takao Moriwaki, Yutaka Yoshii, Takayuki Fujii, Jun Otsuji, Yoshinobu Sasaki, Yukio Miyazaki, Kazuo Nishitani

Proceedings of the ASP-DAC '98, 1998

1991

A 5-ns GaAs 16-kb SRAM.

Shuichi Matsue, Hiroshi Makino, Minoru Noda, Hirofumi Nakano, Satoshi Takano, Kazuo Nishitani, Shimpei Kayano

IEEE J. Solid State Circuits, October, 1991

1990

A 7-ns/850-mW GaAs 4-kb SRAM with little dependence on temperature.

Hiroshi Makino, Shuichi Matsue, Minoru Noda, Noriyuki Tanino, Satoshi Takano, Kazuo Nishitani, Shimpei Kayano

IEEE J. Solid State Circuits, October, 1990