Hirofumi Nakano

According to our database, Hirofumi Nakano authored at least 15 papers between 1994 and 2017.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2017

Theoretical Analysis of Activity Cliffs among Benzofuranone-Class Pim1 Inhibitors Using the Fragment Molecular Orbital Method with Molecular Mechanics Poisson-Boltzmann Surface Area (FMO+MM-PBSA) Approach.

Chiduru Watanabe, Hirofumi Watanabe, Kaori Fukuzawa, Lorien J. Parker, Yoshio Okiyama, Hitomi Yuki, Shigeyuki Yokoyama, Hirofumi Nakano, Shigenori Tanaka, Teruki Honma

J. Chem. Inf. Model., December, 2017

2014

A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation.

Yohei Nakata, Yuta Kimi, Shunsuke Okumura, Jinwook Jung, Takuya Sawada, Taku Toshikawa, Makoto Nagata, Hirofumi Nakano, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Hiroyuki Kawai, Hiroshi Kawaguchi, Masahiko Yoshimoto

IEICE Trans. Electron., 2014

A 40-nm resilient cache memory for dynamic variation tolerance with bit-enhancing memory and on-chip diagnosis structures delivering ×91 failure rate improvement.

Yohei Nakata, Yuta Kimi, Shunsuke Okumura, Jinwook Jung, Takuya Sawada, Taku Toshikawa, Makoto Nagata, Hirofumi Nakano, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Hiroyuki Kawai, Hiroshi Kawaguchi, Masahiko Yoshimoto

Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

2012

A stable chip-ID generating physical uncloneable function using random address errors in SRAM.

Hidehiro Fujiwara, Makoto Yabuuchi, Yasumasa Tsukamoto, Hirofumi Nakano, Toru Owada, Hiroyuki Kawai, Koji Nii

Proceedings of the IEEE 25th International SOC Conference, 2012

2011

A Parallelizing Compiler Cooperative Heterogeneous Multicore Processor Architecture.

Yasutaka Wada, Akihiro Hayashi, Takeshi Masuura, Jun Shirako, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara

Trans. High Perform. Embed. Archit. Compil., 2011

2010

Dependable SRAM with enhanced read-/write-margins by fine-grained assist bias control for low-voltage operation.

Koji Nii, Makoto Yabuuchi, Hidehiro Fujiwara, Hirofumi Nakano, Kazuya Ishihara, Hiroyuki Kawai, Kazutami Arimoto

Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

2008

Parallelization with Automatic Parallelizing Compiler Generating Consumer Electronics Multicore API.

Takamichi Miyamoto, Saori Asaka, Hiroki Mikami, Masayoshi Mase, Yasutaka Wada, Hirofumi Nakano, Keiji Kimura, Hironori Kasahara

Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2008

2005

Performance Evaluation of Compiler Controlled Power Saving Scheme.

Jun Shirako, Munehiro Yoshida, Naoto Oshiyama, Yasutaka Wada, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara

Proceedings of the High-Performance Computing - 6th International Symposium, 2005

Multigrain parallel processing on compiler cooperative chip multiprocessor.

Keiji Kimura, Yasutaka Wada, Hirofumi Nakano, Takeshi Kodaka, Jun Shirako, Kazuhisa Ishizaka, Hironori Kasahara

Proceedings of the 9th Annual Workshop on Interaction between Compilers and Computer Architectures, 2005

2003

Static Coarse Grain Task Scheduling with Cache Optimization Using OpenMP.

Hirofumi Nakano, Kazuhisa Ishizaka, Motoki Obata, Keiji Kimura, Hironori Kasahara

Int. J. Parallel Program., 2003

2002

Multigrain Automatic Parallelization in Japanese Millennium Project IT21 Advanced Parallelizing Compiler.

Hironori Kasahara, Motoki Obata, Kazuhisa Ishizaka, Keiji Kimura, Hiroki Kaminaga, Hirofumi Nakano, Kouhei Nagasawa, Akiko Murai, Hiroki Itagaki, Jun Shirako

Proceedings of the 2002 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2002), 2002

2001

Bolt tightening control using neural networks.

Toru Fujinaka, Hirofumi Nakano, Sigeru Omatu

Proceedings of the IEEE International Conference on Systems, 2001

2000

Bolt Tightening Using Impact Wrench Based on Neural Networks.

Toru Fujinaka, Hirofumi Nakano, Michifumi Yoshioka, Sigeru Omatu

J. Robotics Mechatronics, 2000

1999

A 12-ps-resolution digital variable-delay macro cell on GaAs 100 K-gates gate array using a meshed air bridge structure.

Akira Ohta, Norio Higashisaka, Tetsuya Heima, Takayuki Hisaka, Hirofumi Nakano, Ryuji Ohmura, Tadashi Takagi, Noriyuki Tanino

IEEE J. Solid State Circuits, 1999

1994

The reversible DNA-alkylating activity of duocarmycin and its analogues.

Akira Asai, Satoru Nagamura, Hiromitsu Saito, Isami Takahashi, Hirofumi Nakano

Nucleic Acids Res., 1994