Kerry Veenstra

According to our database1, Kerry Veenstra authored at least 12 papers between 1998 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

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Bibliography

2022
Deployment Algorithms for Outdoor IOT Networks Over 2.5D Terrain
PhD thesis, 2022

2021
Modeling Communication over Terrain for Realistic Simulation of Outdoor Sensor Network Deployments.
ACM Trans. Model. Perform. Evaluation Comput. Syst., 2021

2020
Grid Partition: an Efficient Greedy Approach for Outdoor Camera IoT Deployments in 2.5D Terrain.
Proceedings of the 29th International Conference on Computer Communications and Networks, 2020

2019
Reproducible Computer Network Experiments: A Case Study Using Popper.
Proceedings of the 2nd International Workshop on Practical Reproducible Evaluation of Computer Systems, 2019

2016
TerrainLOS: An Outdoor Propagation Model for Realistic Sensor Network Simulation.
Proceedings of the 24th IEEE International Symposium on Modeling, 2016

2015
Guiding sensor-node deployment over 2.5D terrain.
Proceedings of the 2015 IEEE International Conference on Communications, 2015

2014
A machine learning framework for TCP round-trip time estimation.
EURASIP J. Wirel. Commun. Netw., 2014

2013
A management suite for a disruption-tolerant wireless network testbed.
Proceedings of the 2013 IFIP/IEEE International Symposium on Integrated Network Management (IM 2013), 2013

2011
A Machine Learning Approach to End-to-End RTT Estimation and its Application to TCP.
Proceedings of 20th International Conference on Computer Communications and Networks, 2011

2000
Programmable memory blocks supporting content-addressable memory.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2000

1998
Optimizations for a Highly Cost-Efficient Programmable Logic Architecture.
Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, 1998

A silicon efficient FLEX 6000 programmable logic architecture.
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998


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