Kimiyoshi Yamasaki

According to our database, Kimiyoshi Yamasaki authored at least 4 papers between 1993 and 2012.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2012

Suppression of Current Collapse of High-Voltage AlGaN/GaN HFETs on Si Substrates by Utilizing a Graded Field-Plate Structure.

Tadayoshi Deguchi, Hideshi Tomita, Atsushi Kamada, Manabu Arai, Kimiyoshi Yamasaki, Takashi Egawa

IEICE Trans. Electron., 2012

1997

Highly integrated three-dimensional MMIC technology applied to novel masterslice GaAs- and Si-MMICs.

Tsuneo Tokumitsu, Makoto Hirano, Kimiyoshi Yamasaki, Chikara Yamaguchi, Kenjiro Nishikawa, Masayoshi Aikawa

IEEE J. Solid State Circuits, 1997

1995

Asynchronous transfer mode switching LSI chips with 10-Gb/s serial I/O ports.

Shigeki Hino, Minoru Togashi, Kimiyoshi Yamasaki

IEEE J. Solid State Circuits, April, 1995

1993

A dynamic routing control based on a genetic algorithm.

Norio Shimamoto, Atsushi Hiramatsu, Kimiyoshi Yamasaki

Proceedings of International Conference on Neural Networks (ICNN'88), San Francisco, CA, USA, March 28, 1993