Ko-Chi Kuo

According to our database1, Ko-Chi Kuo authored at least 30 papers between 2006 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Bibliography

2023
A 12-bit 1GS/s Digital to Analog Converter with Switching-Minimized Monotonic Coding.
Proceedings of the International Conference on Consumer Electronics - Taiwan, 2023

An Area Efficient Analog Front-End for Sensing EEG Signals with MOS Capacitors in 90nm Process.
Proceedings of the International Conference on Consumer Electronics - Taiwan, 2023

2022
A 8-bit 300MHz Domino Based Successive Approximation Register ADC.
Proceedings of the 19th International SoC Design Conference, 2022

A 12-bit 1 GS/s Current Steering DAC with the Appointed and Thermometer Coding Scheme.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

2021
A Novel Linear-Logarithmic Active Pixel CMOS Image Sensor with wide dynamic range.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

A Fast Locking All Digital Delay Locked Loop with wide operating frequency ranged from 0.5 GHz to 1.8 GHz in 40nm Process.
Proceedings of the 18th International SoC Design Conference, 2021

2019
A 10-bit 250 MS/s Binary Search and Two channel SAR ADC by a two-bit per Conversion with Error Tolerance Ability.
Proceedings of the 2019 International SoC Design Conference, 2019

A High Speed Low Power Pipelined SAR Analog to Digital Converter.
Proceedings of the International Conference on IC Design and Technology, 2019

Fast Locking Technique by Using a Programmable Operational Transconductor for a Phase Lock Loop Design.
Proceedings of the International Conference on IC Design and Technology, 2019

A Bio-Sensing System-on-Chip and Software for Smart Clothes.
Proceedings of the IEEE International Conference on Consumer Electronics, 2019

2016
The implementation of HomePlug AV system.
Proceedings of the International Conference on IC Design and Technology, 2016

2015
Power saving technique for thermometer-code digital-to-analog converters.
Proceedings of the 15th International Symposium on Communications and Information Technologies, 2015

A wide-range and harmonic-free SAR all-digital delay locked loop.
Proceedings of the 15th International Symposium on Communications and Information Technologies, 2015

2014
A 5 GHz LC-VCO frequency synthesizer for unlicensed band of WiMAX.
Expert Syst. Appl., 2014

2012
A 120-420 MHz delay-locked loop with multi-band voltage-controlled delay unit.
Int. J. Circuit Theory Appl., 2012

Low power design flow with static and statistical timing analysis.
Proceedings of the International Symposium on Intelligent Signal Processing and Communications Systems, 2012

Power line communication chip design with data error detecting/correcting and data encrypting/decrypting ability.
Proceedings of the International Symposium on Intelligent Signal Processing and Communications Systems, 2012

High linear transconductor for multiband CMOS receiver.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

Low power delay locked loop with all digital controlled SAR delay cell.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2011
A Switching Sequence for Linear Gradient Error Compensation in the DAC Design.
IEEE Trans. Circuits Syst. II Express Briefs, 2011

A 2.4GHz low phase noise frequency synthesizer for WiMAX applications.
IEICE Electron. Express, 2011

2010
Low power and high speed multiplier design with row bypassing and parallel architecture.
Microelectron. J., 2010

A fully digital modulator/demodulator for Power Line Communication (PLC).
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

Low power level shifter and combined with logic gates.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2009
A low voltage, high linear, and tunable triode transconductor.
IEICE Electron. Express, 2009

2008
5 GHz phase locked loop with auto band selection.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2006
A CMOS High-Speed Nine-Stage Programmable Counter.
Proceedings of the International MultiConference of Engineers and Computer Scientists 2006, 2006

A Low-Power Multiplier with Bypassing Logic and Operand Decomposition.
Proceedings of the International MultiConference of Engineers and Computer Scientists 2006, 2006

A 2.4-GHz/5-GHz Low Power Pulse Swallow Counter in 0.18-µm CMOS Technology.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

Low Power Multiplier with Bypassing and Tree Strucuture.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006


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