Krishnan Padmanabhan

According to our database1, Krishnan Padmanabhan authored at least 35 papers between 1983 and 2020.

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Bibliography

2020
Top-Down Control of Inhibitory Granule Cells in the Main Olfactory Bulb Reshapes Neural Dynamics Giving Rise to a Diversity of Computations.
Frontiers Comput. Neurosci., 2020

2015
An Empirical Model for Reliable Spiking Activity.
Neural Comput., 2015

2012
Interleaver Structures for Channel Estimation and Decoding on the Frequency Selective Fading Channel.
IEEE Trans. Commun., 2012

2011
Information Rates for Multiantenna Systems With Unknown Fading.
IEEE Trans. Inf. Theory, 2011

The Sampling Theorem With Constant Amplitude Variable Width Pulses.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

2010
Exact PWM representation of bandlimited signals.
Proceedings of the 2010 IEEE Information Theory Workshop, 2010

Large wireless systems with unknown fading.
Proceedings of the 48th Annual Allerton Conference on Communication, 2010

2009
Information rates of the noncoherent frequency selective fading channel.
Proceedings of the 47th Annual Allerton Conference on Communication, 2009

2008
Tight upper and lower bounds on the constrained capacity of non-coherent multi-antenna channels.
Proceedings of the 2008 IEEE International Symposium on Information Theory, 2008

2006
Calculating and Achieving Capacity on the Unknown Fading MIMO Channel.
Proceedings of the Proceedings 2006 IEEE International Symposium on Information Theory, 2006

2005
General CPM and its capacity.
Proceedings of the 2005 IEEE International Symposium on Information Theory, 2005

1996
On-line adaptive optimal combustor control.
IEEE Trans. Control. Syst. Technol., 1996

1995
An efficient architecture for fault-tolerant ATM switches.
IEEE/ACM Trans. Netw., 1995

1994
Specification of Schedulers Using the Modal-p Calculus.
Aust. Comput. J., 1994

1993
A Shuffle-Based Alternative to the ADM Interconnection Architecture.
J. Parallel Distributed Comput., 1993

1992
Effect of Data Access Delays and System Partitionability on the Dynamic Performance of a Shared Memory Multiprocessor.
Proceedings of the Proceedings Supercomputing '92, 1992

1991
Design and Analysis of Even-Sized Binary Shuffle-Exchange Networks for Multiprocessors.
IEEE Trans. Parallel Distributed Syst., 1991

Efficient Architectures for Data Access in a Shared Memory Hierarchy.
J. Parallel Distributed Comput., 1991

Performance of Multicomputer Networks under Pin-out Constraints.
J. Parallel Distributed Comput., 1991

the Twisted Cube Topology for Multiprocessors: A Study in Network Asymmetry.
J. Parallel Distributed Comput., 1991

On the tradeoff between node degree and communication channel width in shuffle-exchange networks.
Proceedings of the Third IEEE Symposium on Parallel and Distributed Processing, 1991

On Multistage Networks with Ternary Switching Elements.
Proceedings of the International Conference on Parallel Processing, 1991

1990
Cube Structures for Multiprocessors.
Commun. ACM, 1990

A Generalization of the Binary Shuffle-Exchange Architecture for Non-Power-of-Two System Sizes.
Proceedings of the 1990 International Conference on Parallel Processing, 1990

Constraint Based Evaluation of Multicomputer Networks.
Proceedings of the 1990 International Conference on Parallel Processing, 1990

1989
Performance of the Direct Binary n-Cube Network for Multiprocessors.
IEEE Trans. Computers, 1989

The composite binary cube - a family of interconnection networks for multiprocessors.
Proceedings of the 3rd international conference on Supercomputing, 1989

An Analysis of the Twisted Cube Topology.
Proceedings of the International Conference on Parallel Processing, 1989

1988
Reliability of the Hypercube.
Proceedings of the International Conference on Parallel Processing, 1988

Instruction reorganization for a variable-length pipelined microprocessor.
Proceedings of the Computer Design: VLSI in Computers and Processors, 1988

1987
Dilated Networks for Photonic Switching.
IEEE Trans. Commun., 1987

1985
Performance Analysis of Redundant-Path Networks for Multiprocessor Systems
ACM Trans. Comput. Syst., 1985

1984
Fault Tolerance and Performance Improvement in Multiprocessor Interconnection Networks (shuffle-Exchange, Redundant-Path Array Processors)
PhD thesis, 1984

1983
A Class of Redundant Path Multistage Interconnection Networks.
IEEE Trans. Computers, 1983

Fault Tolerance Schemes in Shuffle-Exchange Type Interconnection Networks.
Proceedings of the International Conference on Parallel Processing, 1983


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