Krisztián Flautner

According to our database1, Krisztián Flautner authored at least 50 papers between 1999 and 2014.

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Bibliography

2014
A study of Thread Level Parallelism on mobile devices.
Proceedings of the 2014 IEEE International Symposium on Performance Analysis of Systems and Software, 2014

2011
Correction to "A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation".
J. Solid-State Circuits, 2011

A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation.
J. Solid-State Circuits, 2011

High-Performance Multiprocessor System on Chip: Trends in Chip Architecture for the Mass Market.
Proceedings of the Multiprocessor System-on-Chip - Hardware Design and Tool Integration., 2011

2010
AnySP: Anytime Anywhere Anyway Signal Processing.
IEEE Micro, 2010

A power-efficient 32b ARM ISA processor using timing-error detection and correction for transient-error tolerance and adaptation to PVT variation.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

Evolution of thread-level parallelism in desktop applications.
Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010

Optimize your power and performance yields and regain those sleepless nights.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Addressing design margins through error-tolerant circuits.
Proceedings of the 46th Design Automation Conference, 2009

Life on the Treadmill.
Proceedings of the Architecture of Computing Systems, 2009

2008
Introduction to embedded systems week 2006 special issue.
ACM Trans. Embedded Comput. Syst., 2008

PicoServer: Using 3D stacking technology to build energy efficient servers.
JETC, 2008

The State of ESL Design [Roundtable].
IEEE Design & Test of Computers, 2008

Energy-Efficient Simultaneous Thread Fetch from Different Cache Levels in a Soft Real-Time SMT Processor.
Proceedings of the Embedded Computer Systems: Architectures, 2008

From SODA to scotch: The evolution of a wireless baseband processor.
Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), 2008

Reconfigurable energy efficient near threshold cache architectures.
Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), 2008

The Wall Ahead is Made of Rubber.
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

SoC-C: efficient programming abstractions for heterogeneous multicore systems on chip.
Proceedings of the 2008 International Conference on Compilers, 2008

2007
SODA: A High-Performance DSP Architecture for Software-Defined Radio.
IEEE Micro, 2007

The Next Generation Challenge for Software Defined Radio.
Proceedings of the Embedded Computer Systems: Architectures, 2007

Architectural Trade-Offs for Fault Tolerant Multi-Core Systems.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

Blurring the Layers of Abstractions: Time to Take a Step Back?
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

Liquid SIMD: Abstracting SIMD Hardware using Lightweight Dynamic Mapping.
Proceedings of the 13st International Conference on High-Performance Computer Architecture (HPCA-13 2007), 2007

2006
Design and Implementation of Turbo Decoders for Software Defined Radio.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006

SODA: A Low-power Architecture For Software Radio.
Proceedings of the 33rd International Symposium on Computer Architecture (ISCA 2006), 2006

Topic 18: Embedded Parallel Systems.
Proceedings of the Euro-Par 2006, Parallel Processing, 12th International Euro-Par Conference, Dresden, Germany, August 28, 2006

Cutting across layers of abstraction: : removing obstacles from the advancement of embedded systems.
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

PicoServer: using 3D stacking technology to enable a compact energy efficient chip multiprocessor.
Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, 2006

2005
The limit of dynamic voltage scaling and insomniac dynamic voltage scaling.
IEEE Trans. VLSI Syst., 2005

Error Analysis for the Support of Robust Voltage Scaling.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors.
Proceedings of the 32st International Symposium on Computer Architecture (ISCA 2005), 2005

Software Defined Radio - A High Performance Embedded Challenge.
Proceedings of the High Performance Embedded Architectures and Compilers, 2005

Exploring the design space of LUT-based transparent accelerators.
Proceedings of the 2005 International Conference on Compilers, 2005

2004
Circuit and microarchitectural techniques for reducing cache leakage power.
IEEE Trans. VLSI Syst., 2004

Razor: Circuit-Level Correction of Timing Errors for Low-Power Operation.
IEEE Micro, 2004

Making Typical Silicon Matter with Razor.
IEEE Computer, 2004

Extended dynamic voltage scaling for low power design.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

Application-Specific Processing on a General-Purpose Core via Transparent Instruction Set Customization.
Proceedings of the 37th Annual International Symposium on Microarchitecture (MICRO-37 2004), 2004

IEM926: An Energy Efficient SoC with Dynamic Voltage Scaling.
Proceedings of the 2004 Design, 2004

Theoretical and practical limits of dynamic voltage scaling.
Proceedings of the 41th Design Automation Conference, 2004

2003
Leakage Current: Moore's Law Meets Static Power.
IEEE Computer, 2003

Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation.
Proceedings of the 36th Annual International Symposium on Microarchitecture, 2003

2002
Leakage Current Reduction in VLSI Systems.
Journal of Circuits, Systems, and Computers, 2002

Vertigo: Automatic Performance-Setting for Linux.
Proceedings of the 5th Symposium on Operating System Design and Implementation (OSDI 2002), 2002

Drowsy instruction caches: leakage power reduction using dynamic voltage scaling and cache sub-bank prediction.
Proceedings of the 35th Annual International Symposium on Microarchitecture, 2002

Drowsy Caches: Simple Techniques for Reducing Leakage Power.
Proceedings of the 29th International Symposium on Computer Architecture (ISCA 2002), 2002

Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

2001
Automatic performance setting for dynamic voltage scaling.
Proceedings of the MOBICOM 2001, 2001

2000
Thread Level Parallelism and Interactive Performance of Desktop Applications.
Proceedings of the ASPLOS-IX Proceedings of the 9th International Conference on Architectural Support for Programming Languages and Operating Systems, 2000

1999
A high level simulator integrated with the Mirv compiler.
SIGARCH Computer Architecture News, 1999


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