Kwang-Yeob Lee

According to our database1, Kwang-Yeob Lee authored at least 19 papers between 2008 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

2024
Development of Diode Triggering SCR-Based ESD Protection Circuit with Improved Trigger Voltage for Low Voltage Application.
Proceedings of the International Conference on Electronics, Information, and Communication, 2024

2023
Design of Low Drop Out Regulator with High Robustness ESD Protection Circuit Using Current Buffer Structure.
Proceedings of the International Conference on Electronics, Information, and Communication, 2023

2020
Bit-Serial multiplier based Neural Processing Element with Approximate adder tree.
Proceedings of the International SoC Design Conference, 2020

2019
Design of multicycle path accelerator for neural network.
Proceedings of the 2019 International SoC Design Conference, 2019

2018
Optimal Model Analysis for Denoising Monte Calro Rendering Noise.
Proceedings of the International SoC Design Conference, 2018

2017
Implemetation of image classification CNN using multi thread GPU.
Proceedings of the International SoC Design Conference, 2017

2015
A design of a GP-GPU based stream processor for an image processing.
Proceedings of the 38th International Conference on Telecommunications and Signal Processing, 2015

2013
Erratum: Design of high-reliability LDO with current limiting characteristics with built-in new high tolerance ESD protection circuit [IEICE Electronics Express Vol 10 (2013) No 20 pp 20130516].
IEICE Electron. Express, 2013

Design of high-reliability LDO with current limiting characteristics with built-in new high tolerance ESD protection circuit.
IEICE Electron. Express, 2013

Implementation of Improved Census Transform Stereo Matching on a Multicore Processor.
Proceedings of the Multimedia and Ubiquitous Engineering, 2013

Implementation of object recognition and tracking algorithm on real-time basis.
Proceedings of Eurocon 2013, 2013

2012
SCR-based ESD protection device with low trigger and high robustness for I/O clamp.
IEICE Electron. Express, 2012

Design of multi-core rasterizer for parallel processing.
Proceedings of the International SoC Design Conference, 2012

2011
Electrical characteristics of novel ESD protection devices for I/O and power clamp.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2009
Design of SCR-based ESD protection device for power clamp using deep-submicron CMOS technology.
Microelectron. J., 2009

A Design of Multi-threaded Shader Processor with Dual-Phase Pipeline Architecture.
Proceedings of the First International Conference on Advances in Multimedia, 2009

2008
A Design of a 8-Thread Graphics Processor Unit with Variable-Length Instructions.
J. Inform. and Commun. Convergence Engineering, 2008

A Design of a Mobile Graphics Accelerator based on OpenVG 1.0 API.
J. Inform. and Commun. Convergence Engineering, 2008

The design of high holding voltage SCR for whole-chip ESD protection.
IEICE Electron. Express, 2008


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