Leiou Wang

Proceedings of the 15th IEEE International Conference on ASIC, 2023

2020

A Multiple-Measurement Vectors Reconstruction Method for Low SNR Scenarios.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2020

2019

Convolution Accelerator Designs Using Fast Algorithms.

[BibT_eX]

[DOI]

Yulin Zhao

Algorithms, 2019

An Automatically Selective Signal Combining Algorithm and System for Low SNR ECG Signals.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018

A Signum Polarization Fast Eigen-Based Signal Combining Algorithm.

[BibT_eX]

[DOI]

IEEE Trans. Aerosp. Electron. Syst., 2018

A Novel Failure Detection Circuit for SUMPLE Using Variability Index.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2018

A Faster Algorithm for Reducing the Computational Complexity of Convolutional Neural Networks.

[BibT_eX]

[DOI]

Algorithms, 2018

A Novel Dynamic Generalized Opposition-Based Grey Wolf Optimization Algorithm.

[BibT_eX]

[DOI]

Yanzhen Xing

Algorithms, 2018

A Fast Eigen-Based Signal Combining Algorithm by Using CORDIC.

[BibT_eX]

[DOI]

Proceedings of the 26th European Signal Processing Conference, 2018

2017

An Iteration-Based Variable Step-Size Algorithm for Joint Explicit Adaptation of Time Delay.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2017

Intelligent CFAR Detector Based on Support Vector Machine.

[BibT_eX]

[DOI]

IEEE Access, 2017

A gain factor controlled SUMPLE algorithm and system.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016

A Novel Dictionary-Based Method for Test Data Compression Using Heuristic Algorithm.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2016

2015

A PVT-insensitive all digital CMOS time-to-digital converter based on looped delay-line with extension scheme.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014

Low power register files by eliminating redundant read.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2014

Low power address bus encoding using loop prediction.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2014

2013

A new fast median filtering algorithm based on FPGA.

[BibT_eX]

[DOI]