Leonard M. Napolitano Jr.

According to our database1, Leonard M. Napolitano Jr. authored at least 6 papers between 1986 and 1993.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

1993
Multibit Correcting Data Interface for Fault-Tolerant Systems.
IEEE Trans. Computers, 1993

1992
On the efficiency of 'A new efficient algorithm to compute the two-dimensional discrete Fourier transform'.
IEEE Trans. Signal Process., 1992

1990
The Design of a High Performance Packet-Switched Network.
J. Parallel Distributed Comput., 1990

1989
A special-purpose computer for automatic target recognition.
Proceedings of the IEEE International Conference on Acoustics, 1989

Fault-tolerance in a high-speed 2D convolver/correlator: Starloc.
Proceedings of the Nineteenth International Symposium on Fault-Tolerant Computing, 1989

1986
A Computer Architecture for Dynamic Finite Element Analysis.
Proceedings of the 13th Annual Symposium on Computer Architecture, Tokyo, Japan, June 1986, 1986


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