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Li Wan

Orcid: 0000-0002-6836-2740

Affiliations:
  • Fudan University, State Key Laboratory of Integrated Chips and Systems, State Key Laboratory of ASIC and System, Shanghai, China
  • Jilin University, China (former)


According to our database1, Li Wan authored at least 4 papers between 2022 and 2026.

Collaborative distances:
  • Dijkstra number2 of six.
  • Erdős number3 of five.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

Online presence:

On csauthors.net:

Bibliography

2026
PCMT: Prioritizing Coherence Message Types for NoC Protocol-Level Deadlock Freedom.
[BibTeX]
[DOI]
Yufan Jia
,
Zhiyuan Zhang
,
Chao Fu
,
Li Wan
,
Jun Han
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2026

2025
BoostTM: Best-effort performance guarantees in best-effort hardware transactional memory for distributed manycore architectures.
[BibTeX]
[DOI]
Li Wan
,
Zhiyuan Zhang
,
Chao Fu
,
Qiang Li
,
Jun Han
J. Syst. Archit., 2025

2024
LockillerTM: Enhancing Performance Lower Bounds in Best-Effort Hardware Transactional Memory.
[BibTeX]
[DOI]
Li Wan
,
Fu Chao
,
Qiang Li
,
Jun Han
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2024

2022
LosaTM: A Hardware Transactional Memory Integrated With a Low-Overhead Scenario-Awareness Conflict Manager.
[BibTeX]
[DOI]
Chao Fu
,
Li Wan
,
Jun Han
IEEE Trans. Parallel Distributed Syst., 2022


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