Maneesh Kumar Pandey

According to our database, Maneesh Kumar Pandey authored at least 5 papers between 2013 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2019

Implications of On-Chip Single-Source Clocking on High-Speed Serial Interfaces in Network SoC.

Maneesh Kumar Pandey, Tuhina Gupta, Pallavi Raj, Rohit Sharma

IEEE Des. Test, 2019

Modeling and Characterization of VBUS Power Discharge for Embedded Superspeed USB Host/Devices.

Maneesh Kumar Pandey, Mohit Goyal, Parul Sharma, Rohit Sharma

Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

2014

An FPGA Based Ecosystem for USBPHY Validation.

Maneesh Kumar Pandey, Shwetank Shekhar, Amit Sinha, Arun Mishra

Proceedings of the 15th International Microprocessor Test and Verification Workshop, 2014

2013

An Approach for In-House USB2.0 Electrical Compliance Testing on Nanoscale SoC.

Maneesh Kumar Pandey, Shwetank Shekhar, Nitin Saxena, Gaurav Kumar Agarwal, Amersh Kumar

Proceedings of the 14th International Workshop on Microprocessor Test and Verification, 2013

USB Validation Challenges on C45SOI & C28NM Technology Products.

Maneesh Kumar Pandey, Atul Gupta, Shwetank Shekhar

Proceedings of the 14th International Workshop on Microprocessor Test and Verification, 2013