Märt Saarepera

According to our database, Märt Saarepera authored at least 11 papers between 1998 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

A Theory of Secure and Efficient Implementation of Electronic Money.

Ahto Buldas, Dirk Draheim, Märt Saarepera

SN Comput. Sci., November, 2023

2022

An Ultra-Scalable Blockchain Platform for Universal Asset Tokenization: Design and Implementation.

Ahto Buldas, Dirk Draheim, Mike Gault, Risto Laanoja, Takehiko Nagumo, Märt Saarepera, Syed Attique Shah, Joosep Simm, Jamie Steiner, Tanel Tammet, Ahto Truu

IEEE Access, 2022

Secure and Efficient Implementation of Electronic Money.

Ahto Buldas, Dirk Draheim, Märt Saarepera

Proceedings of the Future Data and Security Engineering. Big Data, Security and Privacy, Smart City and Industry 4.0 Applications, 2022

Towards a Foundation of Web3.

Ahto Buldas, Dirk Draheim, Mike Gault, Märt Saarepera

Proceedings of the Future Data and Security Engineering. Big Data, Security and Privacy, Smart City and Industry 4.0 Applications, 2022

2017

Are the Current System Engineering Practices Sufficient to Meet Cyber Crime?

Ahto Buldas, Märt Saarepera

Proceedings of the Human Aspects of Information Security, Privacy and Trust, 2017

2006

Rational Choice of Security Measures Via Multi-parameter Attack Trees.

Ahto Buldas, Peeter Laud, Jaan Priisalu, Märt Saarepera, Jan Willemson

Proceedings of the Critical Information Infrastructures Security, 2006

2005

Universally Composable Time-Stamping Schemes with Audit.

Ahto Buldas, Peeter Laud, Märt Saarepera, Jan Willemson

IACR Cryptol. ePrint Arch., 2005

2004

On Provably Secure Time-Stamping Schemes.

Ahto Buldas, Märt Saarepera

Proceedings of the Advances in Cryptology, 2004

2001

Improving the Availability of Time-Stamping Services.

Arne Ansper, Ahto Buldas, Märt Saarepera, Jan Willemson

Proceedings of the Information Security and Privacy, 6th Australasian Conference, 2001

1999

A Self-Timed Implementation of Boolean Functions.

Märt Saarepera, Tomohiro Yoneda

Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '99), 1999

1998

Verification of Parameterized Asynchronous Circuits: A Case Study.

Tomohiro Yoneda, Yutaka Ohtsuka, Märt Saarepera

Proceedings of the 1st International Conference on Application of Concurrency to System Design (ACSD '98), 1998