Martín Gavilánez
Orcid: 0009-0002-5763-0671
According to our database1,
Martín Gavilánez
authored at least 2 papers
between 2024 and 2025.
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Bibliography
2025
Assessment of 2T2R Logic-in-Memory in a Cycle-to-Cycle Variation-Aware Simulation Environment.
Proceedings of the 23rd IEEE Interregional NEWCAS Conference, 2025
2024
A Calibrated Memristor Model Implementation for an SR-Latch Based on CMOS-Memristor Technology.
Proceedings of the 15th IEEE Latin America Symposium on Circuits and Systems, 2024