Ramiro Taco

According to our database, Ramiro Taco authored at least 24 papers between 2014 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

XNOR-Bitcount Operation Exploiting Computing-In-Memory With STT-MRAMs.

Ariana Musello, Esteban Garzón, Marco Lanuzza, Luis-Miguel Prócel, Ramiro Taco

IEEE Trans. Circuits Syst. II Express Briefs, March, 2023

Programmable All-in-One 4×8-/2×16-/1×32-Bits Dual Mode Logic Multiplier in 16 nm FinFET With Semi-Automatic Flow.

Netanel Shavit, Inbal Stanger, Ramiro Taco, Alexander Fish, Itamar Levi

IEEE Access, 2023

Performance Benchmarking of FinFET- and TFET-Based STT-MRAM Bitcells Operating at Ultra-Low Voltages.

Santiago S. Pérez, Alessandro Bedoya, Luis-Miguel Prócel, Ramiro Taco

Proceedings of the 14th IEEE Latin America Symposium on Circuits and System, 2023

2022

A Method for Mitigation of Droop Timing Errors Including a 500 MHz Droop Detector and Dual Mode Logic.

Yizhak Shifman, Inbal Stanger, Netanel Shavit, Ramiro Taco, Alexander Fish, Joseph Shor

IEEE J. Solid State Circuits, 2022

DMTJ-Based Non-Volatile Ternary Content Addressable Memory for Energy-Efficient High-Performance Systems.

Kevin Vicuña, Luis-Miguel Prócel, Lionel Trojman, Ramiro Taco

Proceedings of the 13th IEEE Latin America Symposium on Circuits and System, 2022

Energy-Efficient FinFET-Versus TFET-Based STT-MRAM Bitcells.

Ariana Musello, Santiago S. Pérez, Marco Villegas, Luis-Miguel Prócel, Ramiro Taco, Lionel Trojman

Proceedings of the 13th IEEE Latin America Symposium on Circuits and System, 2022

Voltage and Technology Scaling of DMTJ-based STT-MRAMs for Energy-Efficient Embedded Memories.

Esteban Garzón, Ramiro Taco, Luis-Miguel Prócel, Lionel Trojman, Marco Lanuzza

Proceedings of the 13th IEEE Latin America Symposium on Circuits and System, 2022

2021

RF-DC Multiplier for RF Energy Harvester based on 32nm and TFET technologies.

Lionel Trojman, David Rivadeneira, Marco Villegas, Eliana Acurio, Marco Lanuzza, Luis-Miguel Procel, Ramiro Taco

Proceedings of the 12th IEEE Latin America Symposium on Circuits and System, 2021

High-Speed and Low-Energy Dual-Mode Logic based Single-Clack-Cycle Binary Comparator.

Ricardo Escobar, Luis-Miguel Prócel, Lionel Trojman, Marco Lanuzza, Ramiro Taco

Proceedings of the 12th IEEE Latin America Symposium on Circuits and System, 2021

Live Demo: Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths.

Inbal Stanger, Netanel Shavit, Ramiro Taco, Marco Lanuzza, Alexander Fish

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Live Demonstration: A 0.8V, 1.54 pJ / 940 MHz Dual Mode Logic-Based 16x16-Bit Booth Multiplier in 16-nm FinFET.

Netanel Shavit, Inbal Stanger, Ramiro Taco, Marco Lanuzza, Alexander Fish

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020

Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths.

Inbal Stanger, Netanel Shavit, Ramiro Taco, Marco Lanuzza, Alexander Fish

IEEE Trans. Circuits Syst. II Express Briefs, 2020

Reconfigurable CMOS/STT-MTJ Non-Volatile Circuit for Logic-in-Memory Applications.

Esteban Garzón, Benjamin Zambrano, Tatiana Moposita, Ramiro Taco, Luis-Miguel Prócel, Lionel Trojman

Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020

Dual Mode Logic Address Decoder.

Leonid Yavits, Ramiro Taco, Netanel Shavit, Inbal Stanger, Alexander Fish

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Exploiting Single-Well Design for Energy-Efficient Ultra-Wide Voltage Range Dual Mode Logic-Based Digital Circuits in 28nm FD-SOI Technology.

Ramiro Taco, Leonid Yavits, Netanel Shavit, Inbal Stanger, Marco Lanuzza, Alexander Fish

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Robust Dual Mode Pass Logic (DMPL) for Energy Efficiency and High Performance.

Inbal Stanger, Netanel Shavit, Ramiro Taco, Leonid Yavits, Marco Lanuzza, Alexander Fish

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019

An 88-fJ/40-MHz [0.4 V]-0.61-pJ/1-GHz [0.9 V] Dual-Mode Logic 8 × 8 bit Multiplier Accumulator With a Self-Adjustment Mechanism in 28-nm FD-SOI.

Ramiro Taco, Itamar Levi, Marco Lanuzza, Alexander Fish

IEEE J. Solid State Circuits, 2019

Live Demo: An 88fJ / 40 MHz [0.4V] - 0.61pJ / 1GHz [0.9V] Dual Mode Logic 8×8-Bit Multiplier Accumulator with a Self-Adjustment Mechanism in 28 nm FD-SOI.

Ramiro Taco, Itamar Levi, Marco Lanuzza, Alexander Fish

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2017

Evaluation of Dual Mode Logic in 28nm FD-SOI technology.

Ramiro Taco, Itamar Levi, Marco Lanuzza, Alexander Fish

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016

Extended exploration of low granularity back biasing control in 28nm UTBB FD-SOI technology.

Ramiro Taco, Itamar Levi, Marco Lanuzza, Alexander Fish

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015

Ultra-Low-Voltage Self-Body Biasing Scheme and Its Application to Basic Arithmetic Circuits.

Ramiro Taco, Marco Lanuzza, Domenico Albano

VLSI Design, 2015

Gate-level body biasing for subthreshold logic circuits: analytical modeling and design guidelines.

Domenico Albano, Marco Lanuzza, Ramiro Taco, Felice Crupi

Int. J. Circuit Theory Appl., 2015

2014

Dynamic gate-level body biasing for subthreshold digital design.

Marco Lanuzza, Ramiro Taco, Domenico Albano

Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014

Improving speed and power characteristics of pulse-triggered flip-flops.

Marco Lanuzza, Ramiro Taco

Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014