Ramiro Taco

According to our database1, Ramiro Taco authored at least 17 papers between 2014 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2021
RF-DC Multiplier for RF Energy Harvester based on 32nm and TFET technologies.
Proceedings of the 12th IEEE Latin America Symposium on Circuits and System, 2021

High-Speed and Low-Energy Dual-Mode Logic based Single-Clack-Cycle Binary Comparator.
Proceedings of the 12th IEEE Latin America Symposium on Circuits and System, 2021

Live Demo: Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Live Demonstration: A 0.8V, 1.54 pJ / 940 MHz Dual Mode Logic-Based 16x16-Bit Booth Multiplier in 16-nm FinFET.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

Reconfigurable CMOS/STT-MTJ Non-Volatile Circuit for Logic-in-Memory Applications.
Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020

Dual Mode Logic Address Decoder.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Exploiting Single-Well Design for Energy-Efficient Ultra-Wide Voltage Range Dual Mode Logic-Based Digital Circuits in 28nm FD-SOI Technology.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Robust Dual Mode Pass Logic (DMPL) for Energy Efficiency and High Performance.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
An 88-fJ/40-MHz [0.4 V]-0.61-pJ/1-GHz [0.9 V] Dual-Mode Logic 8 × 8 bit Multiplier Accumulator With a Self-Adjustment Mechanism in 28-nm FD-SOI.
IEEE J. Solid State Circuits, 2019

Live Demo: An 88fJ / 40 MHz [0.4V] - 0.61pJ / 1GHz [0.9V] Dual Mode Logic 8×8-Bit Multiplier Accumulator with a Self-Adjustment Mechanism in 28 nm FD-SOI.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2017
Evaluation of Dual Mode Logic in 28nm FD-SOI technology.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
Extended exploration of low granularity back biasing control in 28nm UTBB FD-SOI technology.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
Ultra-Low-Voltage Self-Body Biasing Scheme and Its Application to Basic Arithmetic Circuits.
VLSI Design, 2015

Gate-level body biasing for subthreshold logic circuits: analytical modeling and design guidelines.
Int. J. Circuit Theory Appl., 2015

2014
Dynamic gate-level body biasing for subthreshold digital design.
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014

Improving speed and power characteristics of pulse-triggered flip-flops.
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014


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