Masahiro Kaminaga

According to our database, Masahiro Kaminaga authored at least 15 papers between 2008 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2023

Upper Bound for the Coefficients of the Shortest Vector of Random Lattice.

Masahiro Kaminaga

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., December, 2023

2022

Improving genetic algorithms for solving the SVP: focusing on low memory consumption and high reproducibility.

Masaharu Fukase, Masahiro Kaminaga

Iran J. Comput. Sci., 2022

Random Numbers Generated by the Oscillator Sampling Method as a Renewal Process.

Masahiro Kaminaga

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2022

2020

A True Random Number Generator Method Embedded in Wireless Communication Systems.

Toshinori Suzuki, Masahiro Kaminaga

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2020

2019

Determining the Optimal Random-Padding Size for Rabin Cryptosystems.

Masahiro Kaminaga, Toshinori Suzuki, Masaharu Fukase

IEEE Trans. Inf. Forensics Secur., 2019

2018

Crashing Modulus Attack on Modular Squaring for Rabin Cryptosystem.

Masahiro Kaminaga, Hideki Yoshikawa, Arimitsu Shikoda, Toshinori Suzuki

IEEE Trans. Dependable Secur. Comput., 2018

2015

Double Counting in 2^t-ary RSA Precomputation Reveals the Secret Exponent.

Masahiro Kaminaga, Hideki Yoshikawa, Toshinori Suzuki

IEEE Trans. Inf. Forensics Secur., 2015

2014

Round Addition DFA on SPN Block Ciphers.

Hideki Yoshikawa, Masahiro Kaminaga, Arimitsu Shikoda, Toshinori Suzuki

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

Double Counting in $2^t$-ary RSA Precomputation Reveals the Secret Exponent.

Masahiro Kaminaga, Hideki Yoshikawa, Toshinori Suzuki

CoRR, 2014

Secret key reconstruction method using round addition DFA on lightweight block cipher LBlock.

Hideki Yoshikawa, Masahiro Kaminaga, Arimitsu Shikoda, Toshinori Suzuki

Proceedings of the International Symposium on Information Theory and its Applications, 2014

2013

Round Addition DFA on 80-bit Piccolo and TWINE.

Hideki Yoshikawa, Masahiro Kaminaga, Arimitsu Shikoda, Toshinori Suzuki

IEICE Trans. Inf. Syst., 2013

Round Addition Using Faults for Generalized Feistel Network.

Hideki Yoshikawa, Masahiro Kaminaga, Arimitsu Shikoda

IEICE Trans. Inf. Syst., 2013

Round addition DFA for microcontroller implemented the triple DES.

Hideki Yoshikawa, Masahiro Kaminaga, Arimitsu Shikoda, Toshinori Suzuki

Proceedings of the IEEE 2nd Global Conference on Consumer Electronics, 2013

2011

Development and evaluation of a microstep DFA vulnerability estimation method.

Masahiro Kaminaga, Arimitsu Shikoda, Hideki Yoshikawa

IEICE Electron. Express, 2011

2008

Logic-Level Analysis of Fault Attacks and a Cost-Effective Countermeasure Design.

Masahiro Kaminaga, Takashi Watanabe, Takashi Endo, Toshio Okochi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008