Matteo Chiariello

According to our database1, Matteo Chiariello authored at least 1 paper in 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2025
A 600 MHz, 3.57 ps<sub>R M S</sub> Jitter, 1.84 mW Power Consumption Phase Locked Loop in 12nm FinFET.
Proceedings of the International Conference on IC Design and Technology, 2025


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