Maurício Banaszeski da Silva

According to our database, Maurício Banaszeski da Silva authored at least 4 papers between 2009 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2025

Modeling and Predicting Noise-Induced Failure Rates in Ultra-Low-Voltage SRAM Bitcells Affected by Process Variations.

Léopold Van Brandt, Michele Bonnin, Maurício Banaszeski da Silva, Pascal Bolcato, Gilson I. Wirth, Denis Flandre, Jean-Charles Delvenne

IEEE Trans. Circuits Syst. I Regul. Pap., March, 2025

2023

Random Telegraph Noise in Analog CMOS Circuits.

Maurício Banaszeski da Silva, Gilson I. Wirth, Hans P. Tuinhout, Adrie Zegers-van Duijnhoven, Andries J. Scholten

IEEE Trans. Circuits Syst. I Regul. Pap., 2023

2010

Modeling the impact of RTS on the reliability of ring oscillators.

Maurício Banaszeski da Silva, Gilson I. Wirth

Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010

2009

NBTI-aware technique for transistor sizing of high-performance CMOS gates.

Maurício Banaszeski da Silva, Vinicius V. A. Camargo, Lucas Brusamarello, Gilson I. Wirth, Roberto da Silva

Proceedings of the 10th Latin American Test Workshop, 2009