Mazad S. Zaveri

According to our database, Mazad S. Zaveri authored at least 14 papers between 2008 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

U-UTM: A Cyber-Physical System for Road Traffic Monitoring Using UAVs.

Yagnik M. Bhavsar, Mazad S. Zaveri, Mehul S. Raval, Shaheriar B. Zaveri

Proceedings of the IEEE International Conference on Vehicular Electronics and Safety, 2024

2023

A New Angle Set-Based Absolute Scaling-free Reconfigurable Cordic Algorithm.

Ankur Changela, Mazad Zaveri, Yogesh Kumar

Circuits Syst. Signal Process., December, 2023

A Comparative Study on CORDIC Algorithms and Applications.

Ankur Changela, Mazad Zaveri, Deepak Verma

J. Circuits Syst. Comput., March, 2023

2021

Mixed-radix, virtually scaling-free CORDIC algorithm based rotator for DSP applications.

Ankur Changela, Mazad Zaveri, Deepak Verma

Integr., 2021

2020

FPGA implementation of high-performance, resource-efficient Radix-16 CORDIC rotator based FFT algorithm.

Ankur Changela, Mazad Zaveri, Deepak Verma

Integr., 2020

Experiments with Multinational Cross-Course Project.

Mehul S. Raval, Tolga Kaya, Mazad Zaveri, Paawan Sharma

Proceedings of the IEEE International Conference on Teaching, 2020

2019

Improving the performance of transmission gate and hybrid CMOS Full Adders in chain and tree structure architectures.

Manan Mewada, Mazad Zaveri, Rajesh Amratlal Thakker

Integr., 2019

2018

ASIC Implementation of High Performance Radix-8 CORDIC Algorithm.

Ankur Changela, Mazad Zaveri, Anurag Lakhlani

Proceedings of the 2018 International Conference on Advances in Computing, 2018

2017

Estimating the Maximum Propagation Delay of 4-bit Ripple Carry Adder Using Reduced Input Transitions.

Manan Mewada, Mazad Zaveri, Anurag Lakhlani

Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

2016

A low-power high-speed hybrid full adder.

Manan Mewada, Mazad Zaveri

Proceedings of the 20th International Symposium on VLSI Design and Test, 2016

An input test pattern for characterization of a full-adder and n-bit ripple carry adder.

Manan Mewada, Mazad Zaveri

Proceedings of the 2016 International Conference on Advances in Computing, 2016

2011

Performance/price estimates for cortex-scale hardware: A design space exploration.

Mazad S. Zaveri, Dan W. Hammerstrom

Neural Networks, 2011

2008

CMOS / CMOL architectures for spiking cortical column.

Changjian Gao, Mazad S. Zaveri, Dan W. Hammerstrom

Proceedings of the International Joint Conference on Neural Networks, 2008

Bayesian Memory, a Possible Hardware Building Block for Intelligent Systems.

Dan Hammerstrom, Mazad Zaveri

Proceedings of the Biologically Inspired Cognitive Architectures, 2008