Dan W. Hammerstrom

Affiliations:
  • Portland State University, OR, USA
  • Oregon Graduate Institute, Beaverton, OR, USA
  • University of Illinois at Urbana-Champaign, IL, USA (PhD)


According to our database1, Dan W. Hammerstrom authored at least 27 papers between 1977 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 2011, "For contributions to high performance computer architectures for pattern recognition, image processing, and neural network emulation".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2019
Approximate Pattern Matching using Hierarchical Graph Construction and Sparse Distributed Representation.
Proceedings of the International Conference on Neuromorphic Systems, 2019

2015
Introduction to Special Issue on Neuromorphic Computing.
ACM J. Emerg. Technol. Comput. Syst., 2015

2011
Performance/price estimates for cortex-scale hardware: A design space exploration.
Neural Networks, 2011

Representation, methods, and circuits for time-based conversion and computation.
Int. J. Circuit Theory Appl., 2011

2008
CMOS / CMOL architectures for spiking cortical column.
Proceedings of the International Joint Conference on Neural Networks, 2008

Bayesian Memory, a Possible Hardware Building Block for Intelligent Systems.
Proceedings of the Biologically Inspired Cognitive Architectures, 2008

2007
Cortical Models Onto CMOL and CMOS - Architectures and Performance/Price.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007

Defect-Tolerant CMOL Cell Assignment via Satisfiability
CoRR, 2007

Architectures for Silicon Nanoelectronics and Beyond.
Computer, 2007

2005
A Cohesive FPGA-Based System-on-Chip Design Curriculum.
Proceedings of the 2005 International Conference on Microelectronics Systems Education, 2005

2004
Neural systems integration.
Neurocomputing, 2004

2000
Computational Neurobiology Meets Semiconductor Engineering.
Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic, 2000

1996
Image processing using one-dimensional processor arrays.
Proc. IEEE, 1996

1995
Model Matching and SFMD Computation.
Proceedings of the Advances in Neural Information Processing Systems 8, 1995

1993
Neurocomputing hardware: present and future.
Artif. Intell. Rev., 1993

A neural network systems component.
Proceedings of International Conference on Neural Networks (ICNN'88), San Francisco, CA, USA, March 28, 1993

1991

1990
Hebbian feature discovery improves classifier efficiency.
Proceedings of the IJCNN 1990, 1990

A VLSI architecture for high-performance, low-cost, on-chip learning.
Proceedings of the IJCNN 1990, 1990

1988
An interconnect structure for wafer scale neurocomputers.
Neural Networks, 1988

Fault simulation of a wafer-scale integrated neural network.
Neural Networks, 1988

Why VLSI implementations of associative VLCNs require connection multiplexing.
Proceedings of International Conference on Neural Networks (ICNN'88), 1988

1987
The Connectivity Analysis of Simple Association.
Proceedings of the Neural Information Processing Systems, Denver, Colorado, USA, 1987, 1987

1986
The cognitive architecture project.
SIGARCH Comput. Archit. News, 1986

1982
Supporting Ada Memory Management in the iAPX-432.
Proceedings of the Symposium on Architectural Support for Programming Languages and Operating Systems, 1982

1977
Analysis of Memory Addressing Architecture
PhD thesis, 1977

Information Content of CPU Memory Referencing Behavior.
Proceedings of the 4th Annual Symposium on Computer Architecture, 1977


  Loading...