Mokhtar Aboelaze

According to our database1, Mokhtar Aboelaze authored at least 34 papers between 1987 and 2018.

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Bibliography

2018
A hardware in the loop emulator for a satellite control system.
Int. J. Embed. Syst., 2018

2015
Implementation of multiple PID controllers on FPGA.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

2013
An FPGA based low power multiplier for FFT in OFDM systems using precomputations.
Proceedings of the International Conference on Information and Communication Technology Convergence, 2013

2012
Using Low-power Embedded Microcontrollers as Web Servers.
Proceedings of the 10th IEEE International Symposium on Parallel and Distributed Processing with Applications, 2012

2008
A Call Admission Control Protocol for Multimedia Cellular Networks.
J. Networks, 2008

Energy efficient i-cache using multiple line buffers with prediction.
IET Comput. Digit. Tech., 2008

Routing and Wavelength Assignment in Optical Networks Using Boolean Satisfiability.
Proceedings of the 5th IEEE Consumer Communications and Networking Conference, 2008

2007
Routing in Optical and Non-Optical Networks using Boolean Satisfiability.
J. Commun., 2007

Low Energy I-Cache for Embedded Processors.
Proceedings of the 2007 International Conference on Computer Design, 2007

2006
Modified Hotspot Cache Architecture: A Low Energy Fast Cache for Embedded Processors.
Proceedings of 2006 International Conference on Embedded Computer Systems: Architectures, 2006

Reducing Memory References for FFT Calculation.
Proceedings of the 2006 International Conference on Computer Design & Conference on Computing in Nanotechnology, 2006

2005
Reducing Energy in Instruction Caches by Using Multiple Line Buffers with Prediction.
Proceedings of the High-Performance Computing - 6th International Symposium, 2005

2004
A priority based call admission control protocol with call degradation for cellular networks.
Proceedings of the 1st IEEE International Symposium on Wireless Communication Systems, 2004

Performance Evaluation of a Call Admission Control Protocol for Cellular Networks.
Proceedings of the International Conference on Wireless Networks, 2004

2003
Performance of TCP/UDP under Ad Hoc IEEE802.11
CoRR, 2003

Improving TCP/IP Performance over Wireless IEEE 802.11 Link
CoRR, 2003

A new recursive formulation for 2-D WHT.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Dynamic Channel Adaptive MAC with Frame Length Prediction (DCAM/FLP).
Proceedings of the International Conference on Wireless Networks, 2003

2002
An improved Toom's algorithm for linear convolution.
IEEE Signal Process. Lett., 2002

2001
Dynamic Cell Allocation to Input Queues in a Combined I/O Buffered ATM Switch.
Proceedings of the International Conference on Internet Computing, 2001

2000
The Performance of Ethernet under a Combined Data/Real-Time Traffic.
Proceedings of the Proceedings 27th Conference on Local Computer Networks, 2000

An efficient algorithm for multidimensional convolution.
Proceedings of the IEEE International Conference on Acoustics, 2000

1999
A New Hierarchical Small-Node Degree Interconnection Network.
Proceedings of the 17th IASTED International Conference on Applied Informatics, 1999

1996
MLH: A hierarchical hypercube network.
Networks, 1996

1995
A Processor Array with Bounded I/O Ports for Computing Transitive Closures.
J. Parallel Distributed Comput., 1995

1993
A Method for Data Allocation and Manipulation in Hypercube Computers.
Parallel Comput., 1993

Two-dimensional digital filtering using constant-I/O systolic arrays.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

1991
A Comparative Performace Analysis of Mapping Application to Parallel Mutliprocessor Systems: A Case Study.
J. Parallel Distributed Comput., 1991

Complexities of layouts in three-dimensional VLSI circuits.
Inf. Sci., 1991

Multi-level Hypercube Network.
Proceedings of the Fifth International Parallel Processing Symposium, Proceedings, Anaheim, California, USA, April 30, 1991

A programmable VLSI array with constant I/O pins.
Proceedings of the Algorithms and Parallel VLSI Architectures II, 1991

1989
Delay Analysis of the <i>N</i>-Cube Network.
Proceedings of the Computing in the 90's, 1989

1988
Systematic Designs of Buffers in Macropipelines of Systolic Arrays.
J. Parallel Distributed Comput., 1988

1987
The Mapping of Applications to Multiple Bus and Banyan Interconnected Multiprocessor Systems: A Case Study.
Proceedings of the Supercomputing, 1987


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