Murat Askar

Orcid: 0000-0001-9244-3340

Affiliations:
  • Middle East Technical University


According to our database1, Murat Askar authored at least 14 papers between 1999 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
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PhD thesis 
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Links

Online presence:

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Bibliography

2022
Improved Detection of Broken Rotor Bars by 1-D Self-ONNs.
Proceedings of the IECON 2022, 2022

2018
Heat leakage detection and surveiallance using aerial thermography drone.
Proceedings of the 26th Signal Processing and Communications Applications Conference, 2018

2016
Real-Time Motor Fault Detection by 1-D Convolutional Neural Networks.
IEEE Trans. Ind. Electron., 2016

2010
8×8-Bit multiplier designed with a new wave-pipelining scheme.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2008
Delay insensitivity verification of bit-level pipelined systolic arrays in dual-rail treshold logic.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

SDIVA: Structural Delay Insensitivity Verification Analysis Method for Bit-Level Pipelined Systolic Arrays with Early Output Evaluation.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

2007
Application of Bit-level Pipelining to Delay Insensitive Null Convention Adders.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
CMOS planar spiral inductor modeling and low noise amplifier design.
Microelectron. J., 2006

2004
Two fast RSA implementations using high-radix montgomery algorithm.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A high speed ASIC implementation of the Rijndael algorithm.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Practical performance of planar spiral inductors.
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

A High Speed FPGA Implementation of the Rijndael Algorithm.
Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004

2003
Planar Spiral Inductor Modeling for RFIC Design.
Proceedings of the International Conference on VLSI, 2003

1999
Incremental design of high complexity FIR filters by genetic algorithms.
Proceedings of the ISSPA '99. Proceedings of the Fifth International Symposium on Signal Processing and its Applications, 1999


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