Naresh Shanbhag

According to our database¹, Naresh Shanbhag authored at least 4 papers between 2024 and 2025.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of five.

Awards

IEEE Fellow

IEEE Fellow 2006, "For development of a communication-centric design paradigm for low power systems on a chip.".

Timeline

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Article

PhD thesis

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On csauthors.net:

Bibliography

2025

Compute SNR-Optimal Analog-to-Digital Converters for Analog In-Memory Computing.

[BibT_eX]

[DOI]

Mihir Kavishwar

Naresh Shanbhag

CoRR, July, 2025

Forward Error Correction Requirements for Data Center Connectivity.

[BibT_eX]

[DOI]

Han-Mo Ou

Gene Lee

Naresh Shanbhag

Proceedings of the IEEE Custom Integrated Circuits Conference, 2025

2024

Growing Efficient Accurate and Robust Neural Networks on the Edge.

[BibT_eX]

[DOI]

Vignesh Sundaresha

Naresh Shanbhag

CoRR, 2024

Massive MIMO Signal Detection using SRAM-based In-Memory Computing.

[BibT_eX]

[DOI]

Mihir Kavishwar

Naresh Shanbhag

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

Naresh Shanbhag

Awards

IEEE Fellow

Timeline

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Links

On csauthors.net:

Bibliography

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