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Naresh Shanbhag

According to our database1, Naresh Shanbhag authored at least 7 papers between 2024 and 2026.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 2006, "For development of a communication-centric design paradigm for low power systems on a chip.".

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
Detector-in-Memory for Massive MIMO Detection.
[BibTeX]
[DOI]
Ryan Yuyang Fu
,
Mihir Kavishwar
,
Naresh Shanbhag
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

2025
FedERL: Federated Efficient and Robust Learning for Common Corruptions.
[BibTeX]
[DOI]
Omar Bekdache
,
Naresh Shanbhag
CoRR, August, 2025

Compute SNR-Optimal Analog-to-Digital Converters for Analog In-Memory Computing.
[BibTeX]
[DOI]
Mihir Kavishwar
,
Naresh Shanbhag
CoRR, July, 2025

A Full-system, Programmable, and Extensible In-Memory Computing Simulation Framework for Deep Learning.
[BibTeX]
[DOI]
Kaining Zhou
,
Jian Huang
,
Nam Sung Kim
,
Naresh Shanbhag
Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

Forward Error Correction Requirements for Data Center Connectivity.
[BibTeX]
[DOI]
Han-Mo Ou
,
Gene Lee
,
Naresh Shanbhag
Proceedings of the IEEE Custom Integrated Circuits Conference, 2025

2024
Growing Efficient Accurate and Robust Neural Networks on the Edge.
[BibTeX]
[DOI]
Vignesh Sundaresha
,
Naresh Shanbhag
CoRR, 2024

Massive MIMO Signal Detection using SRAM-based In-Memory Computing.
[BibTeX]
[DOI]
Mihir Kavishwar
,
Naresh Shanbhag
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024


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