Neethu Bal Mallya

According to our database, Neethu Bal Mallya authored at least 4 papers between 2015 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2025

A Performance Analysis of Chiplet-Based Systems.

Neethu Bal Mallya, Panagiotis Strikos, Bhavishya Goel, Ahsen Ejaz, Ioannis Sourdis

Proceedings of the Design, Automation & Test in Europe Conference, 2025

2019

MOESIF: a MC/MP cache coherence protocol with improved bandwidth utilisation.

Geeta Patil, Neethu Bal Mallya, Biju K. Raveendran

Int. J. Embed. Syst., 2019

2015

Way Halted Prediction Cache: An Energy Efficient Cache Architecture for Embedded Processors.

Neethu Bal Mallya, Geeta Patil, Biju K. Raveendran

Proceedings of the 28th International Conference on VLSI Design, 2015

Simulation based Performance Study of Cache Coherence Protocols.

Neethu Bal Mallya, Geeta Patil, Biju K. Raveendran

Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2015