Ioannis Sourdis

According to our database1, Ioannis Sourdis authored at least 68 papers between 2003 and 2020.

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Bibliography

2020
MemSZ: Squeezing Memory Traffic with Lossy Compression.
ACM Trans. Archit. Code Optim., 2020

Hybrid2: Combining Caching and Migration in Hybrid Memory Systems.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020

2019
Decoupled Fused Cache: Fusing a Decoupled LLC with a DRAM Cache.
ACM Trans. Archit. Code Optim., 2019

Energy-Efficient Runtime Management of Heterogeneous Multicores using Online Projection.
ACM Trans. Archit. Code Optim., 2019

LLC-Guided Data Migration in Hybrid Memory Systems.
Proceedings of the 2019 IEEE International Parallel and Distributed Processing Symposium, 2019

AVR: Reducing Memory Traffic with Approximate Value Reconstruction.
Proceedings of the 48th International Conference on Parallel Processing, 2019

Time-SWAD: A Dataflow Engine for Time-Based Single Window Stream Aggregation.
Proceedings of the International Conference on Field-Programmable Technology, 2019

2018
Attacks on Heartbeat-Based Security Using Remote Photoplethysmography.
IEEE J. Biomed. Health Informatics, 2018

DDRNoC: Dual Data-Rate Network-on-Chip.
ACM Trans. Archit. Code Optim., 2018

FreewayNoC: A DDR NoC with Pipeline Bypassing.
Proceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip, 2018

COSSIM: An Open-Source Integrated Solution to Address the Simulator Gap for Systems of Systems.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

FusionCache: Using LLC tags for DRAM cache.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
Enhancing Heart-Beat-Based Security for mHealth Applications.
IEEE J. Biomed. Health Informatics, 2017

Towards real-time whisker tracking in rodents for studying sensorimotor disorders.
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

Modeling energy-performance tradeoffs in ARM big.LITTLE architectures.
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

Odd-ECC: on-demand DRAM error correcting codes.
Proceedings of the International Symposium on Memory Systems, 2017

SWAS: Stealing Work Using Approximate System-Load Information.
Proceedings of the 46th International Conference on Parallel Processing Workshops, 2017

Single window stream aggregation using reconfigurable hardware.
Proceedings of the International Conference on Field Programmable Technology, 2017

2016
RQNoC: A Resilient Quality-of-Service Network-on-Chip with Service Redirection.
ACM Trans. Embed. Comput. Syst., 2016

Resilient Chip Multiprocessors with Mixed-Grained Reconfigurability.
IEEE Micro, 2016

BrainFrame: A node-level heterogeneous accelerator platform for neuron simulations.
CoRR, 2016

Performance analysis of accelerated biophysically-meaningful neuron simulations.
Proceedings of the 2016 IEEE International Symposium on Performance Analysis of Systems and Software, 2016

ECOSCALE: Reconfigurable computing and runtime system for future exascale systems.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Secure key-exchange protocol for implants using heartbeats.
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

Runtime management of adaptive MPSoCs for graceful degradation.
Proceedings of the 2016 International Conference on Compilers, 2016

2015
On Using a Von Neumann Extractor in Heart-Beat-Based Security.
Proceedings of the 2015 IEEE TrustCom/BigDataSE/ISPA, 2015

Secure Hardware-Software Architectures for Robust Computing Systems.
Proceedings of the E-Democracy - Citizen Rights in the World of the New Computing Paradigms, 2015

Reducing the performance overhead of resilient CMPs with substitutable resources.
Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015

2014
Design and Analysis of Binary Tree Static Random Access Memory for Low Power Embedded Systems.
J. Low Power Electron., 2014

Real-Time Olivary Neuron Simulations on Dataflow Computing Machines.
Proceedings of the Supercomputing - 29th International Conference, 2014

The DeSyRe Runtime Support for Fault-Tolerant Embedded MPSoCs.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2014

A Dependable Coarse-Grain Reconfigurable Multicore Array.
Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014

Adaptive entity-identifier generation for IMD emergency access.
Proceedings of the First Workshop on Cryptography and Security in Computing Systems, 2014

FPGA-based biophysically-meaningful modeling of olivocerebellar neurons.
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

Peak misdetection in heart-beat-based security: Characterization and tolerance.
Proceedings of the 36th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2014

A runtime manager for gracefully degrading SoCs.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

A probabilistic analysis of resilient reconfigurable designs.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014


2013
Heuristic search for adaptive, defect-tolerant multiprocessor arrays.
ACM Trans. Embed. Comput. Syst., 2013

A system architecture, processor, and communication protocol for secure implants.
ACM Trans. Archit. Code Optim., 2013

DeSyRe: On-demand system reliability.
Microprocess. Microsystems, 2013

Guest editorial: Workshop on Reconfigurable Computing.
J. Syst. Archit., 2013

on-Demand system reliability: The DeSyRe project.
Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013

Special session on "Fault-tolerant techniques for computer systems, architectures and processors".
Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013

Design techniques of future reliable SoCs.
Proceedings of the 2nd Mediterranean Conference on Embedded Computing, 2013

Software Modification Aided Transient Error Tolerance for Embedded Systems.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2012
The DeSyRe Project: On-Demand System Reliability.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

2011
Communication service for hardware tasks executed on dynamic and partial reconfigurable resources.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

Hardware OS Communication Service and Dynamic Memory Management for RSoCs.
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

Reconfigurable acceleration and dynamic partial self-reconfiguration in general purpose computing.
Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

Longest Prefix Match and updates in Range Tries.
Proceedings of the 22nd IEEE International Conference on Application-specific Systems, 2011

2010
Fine-grain fault diagnosis for FPGA logic blocks.
Proceedings of the International Conference on Field-Programmable Technology, 2010

General Purpose Computing with Reconfigurable Acceleration.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

2009
Range Tries for scalable address lookup.
Proceedings of the 2009 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2009

2008
Regular Expression Matching in Reconfigurable Hardware.
J. Signal Process. Syst., 2008

Scalable Multigigabit Pattern Matching for Packet Inspection.
IEEE Trans. Very Large Scale Integr. Syst., 2008

2007
Designs and algorithms for packet and content inspection.
PhD thesis, 2007

FLUX interconnection networks on demand.
J. Syst. Archit., 2007

Synthesis of Regular Expressions Targeting FPGAs: Current Status and Open Issues.
Proceedings of the Reconfigurable Computing: Architectures, 2007

2006
FLUX Networks: Interconnects on Demand.
Proceedings of 2006 International Conference on Embedded Computer Systems: Architectures, 2006

Reconfigurable Fabric Interconnects.
Proceedings of the International Symposium on System-on-Chip, 2006

Reconfigurable FLUX networks.
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

Regular expression matching for reconfigurable packet inspection.
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

Packet pre-filtering for network intrusion detection.
Proceedings of the 2006 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2006

2005
A Reconfigurable Perfect-Hashing Scheme for Packet Inspection.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

2004
Pre-Decoded CAMs for Efficient and High-Speed NIDS Pattern Matching.
Proceedings of the 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 2004

2003
An Efficient, Low-Cost I/O Subsystem for Network Processors.
IEEE Des. Test Comput., 2003

Fast, Large-Scale String Match for a 10Gbps FPGA-Based Network Intrusion Detection System.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003


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