Nilesh Goel
Orcid: 0000-0001-8406-7867
  According to our database1,
  Nilesh Goel
  authored at least 12 papers
  between 2014 and 2025.
  
  
Collaborative distances:
Collaborative distances:
Timeline
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Bibliography
  2025
    Integr., 2025
    
  
  2024
    Integr., January, 2024
    
  
  2022
Enabling efficient rate and temporal coding using reliability-aware design of a neuromorphic circuit.
    
  
    Int. J. Circuit Theory Appl., December, 2022
    
  
    Integr., 2022
    
  
    Int. J. Circuit Theory Appl., 2022
    
  
Investigating the impact of BTI, HCI and time-zero variability on neuromorphic spike event generation circuits.
    
  
    CoRR, 2022
    
  
Design and Mathematical Modelling of Inter Spike Interval of Temporal Neuromorphic Encoder for Image Recognition.
    
  
    CoRR, 2022
    
  
  2020
    Integr., 2020
    
  
  2018
Correlation of Dynamic and Static Metrics of SRAM Cell under Time-Zero Variability and After NBTI Degradation.
    
  
    Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2018
    
  
  2015
Combined trap generation and transient trap occupancy model for time evolution of NBTI during DC multi-cycle and AC stress.
    
  
    Proceedings of the IEEE International Reliability Physics Symposium, 2015
    
  
Impact of time-zero and NBTI variability on sub-20nm FinFET based SRAM at low voltages.
    
  
    Proceedings of the IEEE International Reliability Physics Symposium, 2015
    
  
  2014
A comprehensive modeling framework for gate stack process dependence of DC and AC NBTI in SiON and HKMG p-MOSFETs.
    
  
    Microelectron. Reliab., 2014