Paolo Paletti

According to our database, Paolo Paletti authored at least 5 papers between 2016 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2019

Steep Subthreshold Swing Originating from Gate Delay.

Paolo Paletti, Mina Asghari Heidarlou, Karla González-Serrano, Cristobal Alessandri, Alan C. Seabaugh

Proceedings of the Device Research Conference, 2019

Dynamics of Ferroelectric and Ionic Memories: Physics and Applications.

Alan C. Seabaugh, Paolo Paletti, Anwesha Palit, Karla González-Serrano, Pratyush Pandey

Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018

Electric Double Layer Esaki Tunnel Junction in a 40-nm-Length, WSe2 Channel Grown by Molecular Beam Epitaxy on Al203.

Paolo Paletti, Alan C. Seabaugh, Ruoyu Yue, Christopher L. Hinkle

Proceedings of the 48th European Solid-State Device Research Conference, 2018

Supercapacity (>1000 fJF/cm²) charge release in a CVD-grown WSe2 FET incorporating a PEO: CsCI04 side gate.

Mina Asghari Heidarlou, B. Jariwala, Paolo Paletti, S. Rouvimov, J. A. Robinsorr, Susan K. Fullerton-Shirey, Alan C. Seabaugh

Proceedings of the 76th Device Research Conference, 2018

2016

Steep slope transistors: Tunnel FETs and beyond.

Alan C. Seabaugh, Cristobal Alessandri, Mina Asghari Heidarlou, Hua-Min Li, Leitao Liu, Hao Lu, Sara Fathipour, Paolo Paletti, Pratyush Pandey, Trond Ytterdal

Proceedings of the 46th European Solid-State Device Research Conference, 2016