Parveen Nisha

According to our database, Parveen Nisha authored at least 4 papers between 2024 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2025

Digital Twin-Based Architecture for Run-Time Power Modeling for Sensorless Edge Devices.

Parveen Nisha, Ratnala Vinay, Kartik Laad, Amit Acharyya

Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

Digital Twin Assisted Performance Aware Power Management for FPGA MPSoC using High Speed Reinforcement Learning.

Kartik Laad, Ratnala Vinay, Parveen Nisha, Vidhumouli Hunsigida, Appa Rao Nali, Amit Acharyya

Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

2024

Digital Twin Based Run Time Power Management for Edge SoC using Performance Aware Reinforcement Learning.

Ratnala Vinay, Kartik Laad, Parveen Nisha, Afreen Aijaz, Bhavya Pisipati, Pradip Sasmal, Toshihisa Haraki, Chirag Juyal, Yuki Tanimoto, Amit Acharyya

Proceedings of the 37th IEEE International System-on-Chip Conference, 2024

Run-Time Prevention of Thermal Throttling on the Edge using Reinforcement-Learning Based Predictive Thermal Aware Power and Performance Management.

Parveen Nisha, Ratnala Vinay, Kartik Laad, Pradip Sasmal, Toshihisa Haraki, Chirag Juyal, Mohamed Amir Gabir Elbakri, Amit Acharyya

Proceedings of the 22nd IEEE Interregional NEWCAS Conference, 2024