Patroklos Pazionis

According to our database1, Patroklos Pazionis authored at least 1 paper in 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2025
A 4.8ps Resolution, PVT-insensitive Vernier-based TDC using switched-RO PLL and Back Gate Calibration.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2025


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