Paul J. Murtagh

According to our database1, Paul J. Murtagh authored at least 2 papers between 1995 and 1997.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

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Bibliography

1997
A Reconfigurable Bit-Serial VLSI Systolic Array Neuro-Chip.
J. Parallel Distributed Comput., 1997

1995
A reconfigurable VLSI systolic array processor for artificial neural networks / Paul Murtagh
PhD thesis, 1995


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