Peijuan Ju

According to our database, Peijuan Ju authored at least 4 papers between 2023 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2025

An SSF-Based Fast-Transient LDO as Reference Buffer for a 12-Bit 50-MS/s SAR ADC in 40-nm CMOS.

Peijuan Ju, Dixian Zhao, Qisong Wu

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2025

2024

A Packaged 54-to-69-GHz Wideband 2T2R FMCW Radar Transceiver Employing Cascaded-PLL Topology and PTAT-Enhanced Temperature Compensation in 40-nm CMOS.

Chenyu Xu, Xiaofei Liao, Mengru Yang, Feifan Hong, Peijuan Ju, Wendi Chen, Pengfei Diao, Hao Gong, Xiang Liu, Xiaohu You, Dixian Zhao

IEEE J. Solid State Circuits, October, 2024

Multiple-Loop Analysis and Design for Fast-Transient Capacitor-less LDO with Dual-Path Compensation and Zero-Pole placement in 65-nm CMOS.

Peijuan Ju, Qisong Wu, Dixian Zhao

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2024

2023

A 54-to-69-GHz Wideband 2T2R FMCW Radar Transceiver Employing Cascaded-PLL Topology and PTAT-Enhanced Temperature Compensation in 40-nm CMOS.

Chenyu Xu, Xiaofei Liao, Feifan Hong, Mengru Yang, Peijuan Ju, Wendi Chen, Pengfei Diao, Hao Gong, Xiang Liu, Xiaohu You, Dixian Zhao

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023