Peter T. Breuer

According to our database1, Peter T. Breuer authored at least 77 papers between 1989 and 2019.

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Bibliography

2019
Fully encrypted high-speed microprocessor architecture: the secret computer in simulation.
IJCCBS, 2019

Safe Compilation for Encrypted Computing.
IACR Cryptol. ePrint Arch., 2019

Chaotic Compilation for Encrypted Computing: Obfuscation but Not in Name.
IACR Cryptol. ePrint Arch., 2019

An Information Obfuscation Calculus for Encrypted Computing.
IACR Cryptol. ePrint Arch., 2019

Safe and Chaotic Compilation for Hidden Deterministic Hardware Aliasing.
CoRR, 2019

Compiled Obfuscation for Data Structures in Encrypted Computing.
CoRR, 2019

Safe Compilation for Hidden Deterministic Hardware Aliasing and Encrypted Computing.
CoRR, 2019

Chaotic Compilation: A (Statistical) Cloak for a Secret Computer.
Proceedings of the IEEE International Symposium on Software Reliability Engineering Workshops, 2019

Safe Compilation for Hidden Deterministic Hardware Aliasing.
Proceedings of the IEEE International Symposium on Software Reliability Engineering Workshops, 2019

2018
(Un)Encrypted Computing and Indistinguishability Obfuscation.
CoRR, 2018

Superscalar Encrypted RISC: The Measure of a Secret Computer.
Proceedings of the 17th IEEE International Conference On Trust, 2018

On Security in Encrypted Computing.
Proceedings of the Information and Communications Security - 20th International Conference, 2018

The Secret Processor Will Go to the Ball: Benchmark Insider-Proof Encrypted Computing.
Proceedings of the 2018 IEEE European Symposium on Security and Privacy Workshops, 2018

2017
An Obfuscating Compiler.
IACR Cryptol. ePrint Arch., 2017

On Obfuscating Compilation for Encrypted Computing.
Proceedings of the 14th International Joint Conference on e-Business and Telecommunications (ICETE 2017), 2017

Encrypted computing: Speed, security and provable obfuscation against insiders.
Proceedings of the International Carnahan Conference on Security Technology, 2017

2016
Superscalar Encrypted RISC: A Secret Computer in Simulation.
IACR Cryptol. ePrint Arch., 2016

On the Security of Practical and Complete Homomorphic Encrypted Computation.
IACR Cryptol. ePrint Arch., 2016

A Practical Encrypted Microprocessor.
Proceedings of the 13th International Joint Conference on e-Business and Telecommunications (ICETE 2016), 2016

A Fully Encrypted Microprocessor The Secret Computer is Nearly Here.
Proceedings of the 7th International Conference on Ambient Systems, 2016

2015
A First Practical Fully Homomorphic Crypto-Processor Design: The Secret Computer is Nearly Here.
CoRR, 2015

Processor Rescue - Safe Coding for Hardware Aliasing.
Proceedings of the Intelligent Software Methodologies, Tools and Techniques, 2015

2014
Open source verification in an anonymous volunteer network.
Sci. Comput. Program., 2014

On the Security of Fully Homomorphic Encryption and Encrypted Computing: Is Division safe?
CoRR, 2014

Empirical Patterns in Google Scholar Citation Counts.
Proceedings of the 8th IEEE International Symposium on Service Oriented System Engineering, 2014

Avoiding Hardware Aliasing: Verifying RISC Machine and Assembly Code for Encrypted Computing.
Proceedings of the 25th IEEE International Symposium on Software Reliability Engineering Workshops, 2014

Idea: Towards a Working Fully Homomorphic Crypto-processor - Practice and the Secret Computer.
Proceedings of the Engineering Secure Software and Systems - 6th International Symposium, 2014

2013
Towards Proving RISC Machine Code not Risky with respect to Memory Aliasing
CoRR, 2013

Soundness and Completeness of the NRB Verification Logic.
Proceedings of the Software Engineering and Formal Methods, 2013

Certifying Machine Code Safe from Hardware Aliasing: RISC is Not Necessarily Risky.
Proceedings of the Software Engineering and Formal Methods, 2013

A Fully Homomorphic Crypto-Processor Design.
Proceedings of the Engineering Secure Software and Systems - 5th International Symposium, 2013

2012
Typed Assembler for a RISC Crypto-Processor.
Proceedings of the Engineering Secure Software and Systems - 4th International Symposium, 2012

2010
A formal nethod (a networked formal method).
ISSE, 2010

Open Source Verification under a Cloud.
ECEASST, 2010

Special issue: Open Source Certification.
Comput. Syst. Sci. Eng., 2010

2008
Approximate verification in an open source world.
ISSE, 2008

2007
Verification in the Light and Large: Large-Scale Verification for Fast-Moving Open Source C Projects.
Proceedings of the 31st Annual IEEE / NASA Software Engineering Workshop (SEW-31 2007), 2007

2006
Raiding the Noosphere: the open development of networked RAID support for the Linux kernel.
Softw. Pract. Exp., 2006

Symbolic approximation: an approach to verification in the large.
ISSE, 2006

Detecting Deadlock, Double-Free and Other Abuses in a Million Lines of Linux Kernel Source.
Proceedings of the 30th Annual IEEE / NASA Software Engineering Workshop (SEW-30 2006), 2006

Verification in the Large via Symbolic Approximation.
Proceedings of the Leveraging Applications of Formal Methods, 2006

Checking for Deadlock, Double-Free and Other Abuses in the Linux Kernel Source Code.
Proceedings of the Computational Science, 2006

One Million (LOC) and Counting: Static Analysis for Errors and Vulnerabilities in the Linux Kernel Source Code.
Proceedings of the Reliable Software Technologies, 2006

2005
Intelligent Networked Software RAID.
Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Networks, 2005

Dependable Networked RAID for the Open Source Community.
Proceedings of the 11th International Conference on Parallel and Distributed Systems, 2005

2004
Static Deadlock Detection in the Linux Kernel.
Proceedings of the Reliable Software Technologies, 2004

2003
MSC-based Language for Specifying Automated Web Clients.
Proceedings of the Eighth IEEE Symposium on Computers and Communications (ISCC 2003), 30 June, 2003

Building Wrapper Agents for the Deep Web.
Proceedings of the Web Engineering, International Conference, 2003

A Formal Model for the Block Device Subsystem of the Linux Kernel.
Proceedings of the Formal Methods and Software Engineering, 2003

Fault-Tolerant Distributed Mass Storage for LHC Computing.
Proceedings of the 3rd IEEE International Symposium on Cluster Computing and the Grid (CCGrid 2003), 2003

Automation of the Deep Web with User Defined Behaviours.
Proceedings of the Web Intelligence, 2003

2002
Higher Order Applicative XML Documents.
Proceedings of the Radical Innovations of Software and Systems Engineering in the Future, 2002

2001
JCCM: Flexible Certificates for Smartcards with Java Card.
Proceedings of the Smart Card Programming and Security, 2001

1999
Reasoning about VHDL and VHDL-AMS using Denotational Semantics.
Proceedings of the 1999 Design, 1999

1998
The Computational Description of Analogue System Behaviour.
Proceedings of the Prospects for Hardware Foundations, ESPRIT Working Group 8533, NADA, 1998

1997
A Refinement Calculus for the Synthesis of Verified Hardware Descriptions in VHDL.
ACM Trans. Program. Lang. Syst., 1997

A semantic model for VHDL-AMS.
Proceedings of the Advances in Hardware Design and Verification, 1997

1996
A refinement calculus for VHDL.
Proceedings of the conference on European design automation, 1996

A Formal Method for Specification and Refinement of Real-Time Systems.
Proceedings of the Eighth Euromicro Workshop on Real-Time Systems, 1996

1995
A PREttier Compiler-Compiler: Generating Higher-order Parsers in C.
Softw. Pract. Exp., 1995

A Simple Denotational Semantics, Proof Theory and a Validation Condition Generator for Unit-Delay VHDL.
Formal Methods Syst. Des., 1995

A native process algebra for VHDL.
Proceedings of the Proceedings EURO-DAC'95, 1995

1994
Decompilation: The Enumeration of Types and Grammars.
ACM Trans. Program. Lang. Syst., 1994

A software maintenance management model based on queueing networks.
J. Softw. Maintenance Res. Pract., 1994

Towards Correct Executable Semantics for Z.
Proceedings of the Z User Workshop, Cambridge, UK, 29-30 June 1994, Proceedings, 1994

Proving Hardware Designs.
Proceedings of the Logic Programming, 1994

Proof theory and a validation condition generator for VHDL.
Proceedings of the Proceedings EURO-DAC'94, 1994

Clean formal semantics for VHDL.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

1993
Reverse-engineering Cobol via formal methods.
J. Softw. Maintenance Res. Pract., 1993

Formal specifications in software maintenance: from code to Z++ and back again.
Inf. Softw. Technol., 1993

A compendium of formal techniques for software maintenance.
Softw. Eng. J., 1993

1992
Decompilation is the Efficient Enumeration of Types.
Proceedings of the Actes WSA'92 Workshop on Static Analysis (Bordeaux, 1992

The Art of Computer Un-Programming: Reverse Engineering in Prolog.
Proceedings of the Logic Programming in Action, 1992

1991
Creating specifications from code: Reverse-engineering techniques.
J. Softw. Maintenance Res. Pract., 1991

An Analysis/Synthesis Language with Learning Strategies.
Proceedings of the Actes JTASPEFL'91 (Bordeaux, 1991

1990
Z! in Progress: Maintaining Z Specifications.
Proceedings of the Z User Workshop, 1990

1989
From Programs to Z Specifications.
Proceedings of the Fourth Annual Z User Meeting, Oxford, UK, December 15, 1989, 1989


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