Piyali Datta
Orcid: 0000-0002-9470-736X
According to our database1,
Piyali Datta
authored at least 16 papers
between 2014 and 2020.
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Bibliography
2020
A Predictive Model for Fluid-Control Codesign of Paper-Based Digital Biochips Following a Machine Learning Approach.
IEEE Trans. Very Large Scale Integr. Syst., 2020
A Design Optimization for Pin-Constrained Paper-based Digital Microfluidic Biochips Integrating Fluid-Control Co-Design Issues.
Proceedings of the 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, 2020
2019
Fluid-level synthesis unifying reliability, contamination avoidance, and capacity-wastage-aware washing for droplet-based microfluidic biochips.
IET Comput. Digit. Tech., 2019
A Capacity-Aware Wash Optimization for Contamination Removal in Programmable Microfluidic Biochip Devices.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019
2018
A New Fluid-Chip Co-Design for Digital Microfluidic Biochips Considering Cost Drivers and Design Convergence.
IEEE Trans. Multi Scale Comput. Syst., 2018
A low-cost fluid-level synthesis for droplet-based microfluidic biochips integrating design convergence, contamination avoidance, and washing.
Des. Autom. Embed. Syst., 2018
Design Optimization at the Fluid-Level Synthesis for Safe and Low-Cost Droplet-Based Microfluidic Biochips.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018
2017
A Dependability Preserving Fluid-Level Synthesis for Reconfigurable Droplet-Based Microfluidic Biochips.
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017
2016
Multiple parallel assay operations with cross contamination avoidance in a given biochip.
IET Comput. Digit. Tech., 2016
2015
A cost-optimal algorithm for guard zone computation including detection and exclusion of overlapping.
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015
An impressive approach for incorporating parallelism in designing DMFB with cross contamination avoidance.
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015
Proceedings of the Advanced Computing and Systems for Security - ACSS 2015, 2015
Proceedings of the Advanced Computing and Systems for Security - ACSS 2015, 2015
2014
An Algorithm for Parallel Assay Operations in a Restricted Sized Chip in Digital Microfluidics.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014
A 2D Guard Zone Computation Algorithm for Reassignment of Subcircuits to Minimize the Overall Chip Area.
Proceedings of the Applied Computation and Security Systems - ACSS 2014, 2014
A New Move Toward Parallel Assay Operations in a Restricted Sized Chip in Digital Microfluidics.
Proceedings of the Applied Computation and Security Systems - ACSS 2014, 2014