Qui-Ting Chen

According to our database, Qui-Ting Chen authored at least 2 papers between 2009 and 2014.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2014

26.6 A 2.667Gb/s DDR3 memory interface with asymmetric ODT on wirebond package and single-side-mounted PCB.

Shang-Ping Chen, Chih-Chien Hung, Qui-Ting Chen, Sheng-Ming Chang, Ming-Shi Liou, Bo-Wei Hsieh, Hsiang-I Huang, Brian Liu, Yan-Bin Luo

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2009

A 250Mb/s-to-3.4Gb/s HDMI receiver with adaptive loop updating frequencies and an adaptive equalizer.

Yan-Bin Luo, Ping Chen, Qui-Ting Chen, Chih-Yong Wang, Chan-Hao Chang, Szu-Jui Fu, Chien-Ming Chen, Hung-Sung Li

Proceedings of the IEEE International Solid-State Circuits Conference, 2009