R. Seshasayanan

According to our database, R. Seshasayanan authored at least 12 papers between 2005 and 2023.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2023

High performance fir filter based on vedic mathematics.

N. Mohana Priya, C. Bennila Thangammal, R. Seshasayanan, Sheryl Radley

Int. J. Syst. Assur. Eng. Manag., June, 2023

2022

Medical image DENOISING scheme using discrete wavelet transform and optimization with different noises.

T. E. Aravindan, R. Seshasayanan

Concurr. Comput. Pract. Exp., 2022

2021

An efficient field-programmable gate array-based hardware oriented block motion estimation algorithm based on diamond adaptive rood pattern search algorithm for multi-standard video codec.

S. M. Balamurugan, R. Seshasayanan

Trans. Inst. Meas. Control, 2021

2020

Low power single precision BCD floating-point Vedic multiplier.

V. Ramya, R. Seshasayanan

Microprocess. Microsystems, 2020

Development of Combinational Circuits by Encoding on the Basis of Developmental Biology.

S. B. Sivasubramaniyan, R. Seshasayanan, N. Ramadass

Comput. Intell. Neurosci., 2020

2019

Energy efficient parallel hybrid adder architecture for 3X generation in radix-8 booth encoding.

R. Nirmaladevi, R. Seshasayanan

Clust. Comput., 2019

Optimization of logarithmic converter for LNS based SOC.

ATA Kishore Kumar, R. Seshasayanan

Clust. Comput., 2019

2018

Denoising Brain Images with the Aid of Discrete Wavelet Transform and Monarch Butterfly Optimization with Different Noises.

T. E. Aravindan, R. Seshasayanan

J. Medical Syst., 2018

2015

Implementation of computation-reduced DCT using a novel method.

K. K. Senthilkumar, K. Kunaraj, R. Seshasayanan

EURASIP J. Image Video Process., 2015

2014

Performance of Dual-Polarized DSTTD-IDMA system over correlated frequency selective channels.

K. S. Vishvaksenan, R. Seshasayanan, Sudharssun Subramanian

Comput. Electr. Eng., 2014

2013

Performance of joint transmit scheme assisted multiple-input multiple-output multi-carrier IDMA system.

K. S. Vishvaksenan, R. Seshasayanan, Yuvaraj Krishnamoorthy

Comput. Electr. Eng., 2013

2005

Simulation Analysis of Low Power Synchronous Token Ring Based VLIW processor under GALS Multi-processor technology with improved efficiency.

Arun Vijayaraghavan, M. Kannan, R. Seshasayanan

Proceedings of the 2005 International Conference on Computer Design, 2005