Ram Srinivasan

According to our database1, Ram Srinivasan authored at least 9 papers between 1987 and 2010.

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Bibliography

2010
Extending the Monte Carlo Processor Modeling Technique: Statistical Performance Models of the Niagara 2 Processor.
Proceedings of the 39th International Conference on Parallel Processing, 2010

2009
Implementation and performance modeling of deterministic particle transport (Sweep3D) on the IBM Cell/B.E.
Scientific Programming, 2009

2007
An Idealistic Neuro-PPM Branch Predictor.
J. Instruction-Level Parallelism, 2007

Compiler-Directed Functional Unit Shutdown for Microarchitecture Power Optimization.
Proceedings of the 26th IEEE International Performance Computing and Communications Conference, 2007

2006
Performance modeling using Monte Carlo simulation.
Computer Architecture Letters, 2006

Ultra-Fast CPU Performance Prediction: Extending the Monte Carlo Approach.
Proceedings of the 18th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2006), 2006

2005
MonteSim: a Monte Carlo performance model for in-order microachitectures.
SIGARCH Computer Architecture News, 2005

Fast, Accurate Microarchitecture Simulation Using Statistical Phase Detection.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2005

1987
Motion-Compensated Coder for Videoconferencing.
IEEE Trans. Communications, 1987


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