Ramesh Jayabalan

According to our database, Ramesh Jayabalan authored at least 9 papers between 2014 and 2025.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2025

VLSI Implementation of High-Speed and Area-Efficient Multiplierless Address Generation Architecture for Deinterleaver in WiMAX Applications.

Vivek Karthick Perumal, Ramesh Jayabalan, Eldho Paul, Dhanasekaran Selvaraj

J. Electr. Comput. Eng., 2025

2020

PAPR Reduction in OFDM Systems Using Modified SLM with Different Phase Sequences.

Sanjana Prasad, Ramesh Jayabalan

Wirel. Pers. Commun., 2020

2017

An improved low transition test pattern generator for low power applications.

Govindaraj Vellingiri, Ramesh Jayabalan

Des. Autom. Embed. Syst., 2017

Scaled offset PSO based PTS for PAPR reduction in OFDM systems.

Sanjana Prasad, Research Scholar, Ramesh Jayabalan

Proceedings of the 8th IEEE Annual Ubiquitous Computing, 2017

2015

An Improved Low Complex Hybrid Weighted Bit-Flipping Algorithm for LDPC Codes.

Michaelraj Kingston Roberts, Ramesh Jayabalan

Wirel. Pers. Commun., 2015

A Modified Optimally Quantized Offset Min-Sum Decoding Algorithm for Low-Complexity LDPC Decoder.

Michaelraj Kingston Roberts, Ramesh Jayabalan

Wirel. Pers. Commun., 2015

An improved low-complexity sum-product decoding algorithm for low-density parity-check codes.

Michaelraj Kingston Roberts, Ramesh Jayabalan

Frontiers Inf. Technol. Electron. Eng., 2015

A Power- and Area-Efficient Multirate Quasi-Cyclic LDPC Decoder.

Michaelraj Kingston Roberts, Ramesh Jayabalan

Circuits Syst. Signal Process., 2015

2014

An area efficient and high throughput multi-rate quasi-cyclic LDPC decoder for IEEE 802.11n applications.

Michaelraj Kingston Roberts, Ramesh Jayabalan

Microelectron. J., 2014