Raveena Raikar

According to our database, Raveena Raikar authored at least 6 papers between 2022 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2026

Interconnect-Aware Logic Resynthesis for Multi-Die FPGAs.

Xiaoke Wang, Raveena Raikar, Markus Rein, Ruiqi Chen, Chang Meng, Dirk Stroobandt

CoRR, February, 2026

2024

Routing in 2.5D FPGAs: How long should interposer lines be?

Raveena Raikar, Dirk Stroobandt

Proceedings of the ACM International Workshop on System-Level Interconnect Pathfinding, 2024

Balancing Intra-Die and Inter-Die Placement Optimization in 2.5D FPGA Architectures.

Raveena Raikar, Dirk Stroobandt

Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2024

LiquidMD: Optimizing Inter-die and Intra-die placement for 2.5D FPGA Architectures.

Raveena Raikar, Dirk Stroobandt

Proceedings of the 14th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2024

2023

Modularity Driven Parallel Placement Algorithm for 2.5D FPGA Architectures.

Raveena Raikar, Dirk Stroobandt

Proceedings of the ACM International Workshop on System-Level Interconnect Pathfinding, 2023

2022

Multi-Die Heterogeneous FPGAs: How Balanced Should Netlist Partitioning be?

Raveena Raikar, Dirk Stroobandt

Proceedings of the 24th ACM/IEEE Workshop on System Level Interconnect Pathfinding, 2022