Ravi Motwani

Orcid: 0009-0004-5014-7673

Affiliations:
  • Intel Corporation, Santa Clara, California, USA


According to our database1, Ravi Motwani authored at least 23 papers between 1998 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Graph Enhanced Feature Engineering for Privacy Preserving Recommendation Systems.
Proceedings of the ACM RecSys Challenge 2023, Singapore, 19 September 2023, 2023

2018
Combating Bit Errors From Stuck Cells in Flash Memory Using Novel Information Theory Techniques.
Proceedings of the 2018 International Conference on Computing, 2018

2017
An Upper Bounding Technique on the Error Floor Performance of LDPC Codes.
Proceedings of the 2017 IEEE Global Communications Conference, 2017

2016
Construction of Random Input-Output Codes With Moderate Block Lengths.
IEEE Trans. Commun., 2016

Guest Editorial Channel Modeling, Coding and Signal Processing for Novel Physical Memory Devices and Systems.
IEEE J. Sel. Areas Commun., 2016

2015
Soft decision decoding of RAID stripe for higher endurance of flash memory based solid state drives.
Proceedings of the International Conference on Computing, Networking and Communications, 2015

Estimation of Flash Memory Level Distributions Using Interpolation Techniques for Optimizing the Read Reference.
Proceedings of the 2015 IEEE Global Communications Conference, 2015

Signal processing techniques for ensuring fidelity of back-end signal transmission in flash memory based solid state drives.
Proceedings of the 49th Asilomar Conference on Signals, Systems and Computers, 2015

2013
Design of LDPC coding schemes for exploitation of bit error rate diversity across dies in NAND flash memory.
Proceedings of the International Conference on Computing, Networking and Communications, 2013

2012
Robust decoder architecture for multi-level flash memory storage channels.
Proceedings of the International Conference on Computing, Networking and Communications, 2012

2011
Hierarchical Constrained Coding for Floating-Gate to Floating-Gate Coupling Mitigation in Flash Memory.
Proceedings of the Global Communications Conference, 2011

2010
Reduced-Complexity Soft-Output Viterbi Algorithm for Channels Characterized by Dominant Error Events.
Proceedings of the Global Communications Conference, 2010

2005
Bounds on mutual information rates of noisy channels with timing errors.
Proceedings of the 2005 IEEE International Symposium on Information Theory, 2005

2004
Tree-structured oversampled filterbanks as joint source-channel codes: application to image transmission over erasure channels.
IEEE Trans. Signal Process., 2004

Filter bank frame-expansion with erasures-a para-pseudo inverse based reconstruction.
Proceedings of the 2004 IEEE International Symposium on Information Theory, 2004

Insertion/deletion channels: reduced-state lower bounds on channel capacities.
Proceedings of the 2004 IEEE International Symposium on Information Theory, 2004

A para-pseudo inverse based method for reconstruction of filter bank frame-expanded signals from erasures.
Proceedings of the 2004 International Conference on Image Processing, 2004

2003
Simultaneous zero-tailing of parallel concatenated codes.
IEEE Trans. Inf. Theory, 2003

2-channel oversampled filter banks as joint source-channel codes for erasure channels.
Proceedings of the 2003 International Conference on Image Processing, 2003

Quantized frame expansions based on tree-structured oversampled filter banks for erasure recovery.
Proceedings of the 2003 IEEE International Conference on Acoustics, 2003

2002
Convolutional codes with state information for unequal error protection.
Proceedings of the 2002 IEEE Information Theory Workshop, 2002

Oversampled transforms for channels with erasures.
Proceedings of the 2002 IEEE Information Theory Workshop, 2002

1998
Design of two-channel linear phase orthogonal cyclic filterbanks.
IEEE Signal Process. Lett., 1998


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