Reza Omidi Gosheblagh

Orcid: 0000-0003-4328-1845

Affiliations:
  • University of Zanjan, Electrical Engineering Department, Iran


According to our database1, Reza Omidi Gosheblagh authored at least 10 papers between 2014 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
On the Design of Iterative Approximate Floating-Point Multipliers.
IEEE Trans. Computers, June, 2023

2022
Logarithm-approximate floating-point multiplier.
Microelectron. J., 2022

2021
Design of low power approximate floating-point adders.
Int. J. Circuit Theory Appl., 2021

2020
Low-Power Area-Efficient Fault Tolerant Adder in Current Mode Multi Valued Logic Using Berger Codes.
J. Electron. Test., 2020

2019
An Efficient Current Mode MVL Residue Code Checker for Fault-Tolerant Arithmetic.
J. Circuits Syst. Comput., 2019

2018
Novel Metamaterial Compact Planar MIMO Antenna Systems with Improved Isolation for WLAN Application.
Wirel. Pers. Commun., 2018

New Protection Technique Against Unidirectional MEUs for FIR Filters.
Circuits Syst. Signal Process., 2018

2014
Hybrid time and hardware redundancy to mitigate SEU effects on SRAM-FPGAs: Case study over the MicroLAN protocol.
Microelectron. J., 2014

Seu-Secure Parity Prediction Multiplier on SRAM-Based FPGAs.
J. Circuits Syst. Comput., 2014

Three-Level Management Algorithm to Increase the SEU Emulation Rate in DPR Based Emulators.
J. Electron. Test., 2014


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