Roman P. Bazylevych

Affiliations:
  • Lviv Polytechnic National University, Ukraine


According to our database1, Roman P. Bazylevych authored at least 21 papers between 2000 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

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Bibliography

2023
Solving Large Scale Uniform Traveling Salesman Problem by Using Partial Solution Expansion Method.
Proceedings of the 18th IEEE International Conference on Computer Science and Information Technologies, 2023

2022
Input decomposition by clusterization for symbolic execution.
Proceedings of the 17th IEEE International Conference on Computer Sciences and Information Technologies, 2022

2021
Decomposition of the unit test generation task for parallel computations.
Proceedings of the IEEE 16th International Conference on Computer Sciences and Information Technologies, 2021

A set of nets planarization with two chains of contacts.
Proceedings of the IEEE 16th International Conference on Computer Sciences and Information Technologies, 2021

2020
A Set of Nets Planarization for Electronic Devices' Physical Design Automation.
Proceedings of the IEEE 15th International Conference on Computer Sciences and Information Technologies, 2020

Unit Test Generation in a Cluster Using Parallel Computations and Control Flow Graph Analysis.
Proceedings of the IEEE 15th International Conference on Computer Sciences and Information Technologies, 2020

2019
Power System Islanding by the Hierarchical Clustering.
Proceedings of the IEEE 14th International Conference on Computer Sciences and Information Technologies, 2019

Parallelization of Unit Tests Generation by Control Flow Graph analysis.
Proceedings of the 14th IEEE International Conference on Computer Sciences and Information Technologies, 2019

2016
Topologically-Geometric Routing.
Proceedings of the 18th System Level Interconnect Prediction Workshop, 2016

2015
Algorithms for software clustering and modularization.
Proceedings of the Xth International Scientific and Technical Conference "Computer Sciences and Information Technologies", 2015

2014
The analysis and optimization algorithms of the electronic circuits design.
Proceedings of the 3rd Mediterranean Conference on Embedded Computing, 2014

2013
Tutorial: Macro-modeling for solving SOC physical design automation problems.
Proceedings of the 2013 IEEE International SOC Conference, Erlangen, Germany, 2013

Partitioning optimization by iterative reassignment of the hierarchically built clusters with border elements.
Proceedings of the 2nd Mediterranean Conference on Embedded Computing, 2013

The methodology and algorithms for solving the very large-scale physical design automation problems: Partitioning, packaging, placement and routing.
Proceedings of the 2nd Mediterranean Conference on Embedded Computing, 2013

2011
A Parallel Approach for Solving a Large-Scale Traveling Salesman Problem.
Proceedings of the 5th Indian International Conference on Artificial Intelligence, 2011

2009
A Decomposition Algorithm for Uniform Traveling Salesman Problem.
Proceedings of the 4th Indian International Conference on Artificial Intelligence, 2009

2008
Decomposition and Scanning Optimization Algorithms for TSP.
Proceedings of the International Conference on Theoretical and Mathematical Foundations of Computer Science, 2008

2007
Decomposition Algorithms for Large-scale Clustered TSP.
Proceedings of the 3rd Indian International Conference on Artificial Intelligence, 2007

Partitioning Optimization by Recursive Moves of Hierarchically Built Clusters.
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

2000
Circuit Partitioning for FPGAs by the Optimal Circuit Reduction Method.
VLSI Design, 2000

Hierarchial clasterization, decomposition and multilevel macromodeling - the effective and efficient tools to solve the sigh and very high size combinatorial circuit type problems (abstract only).
Proceedings of the Symposium on Contemporary Computing in Ukraine, 2000


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