Sai Pranav K. R

According to our database, Sai Pranav K. R authored at least 3 papers between 2022 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2025

Inductive GNN-Based Methodology for Accurate and Fast Average Power Estimation of Synthesized ASIC Designs From RTL Simulation Bypassing Gate-Level Simulation.

M. B. Rakesh, Pabitra Das, Sai Pranav K. R, Amit Acharyya

IEEE Trans. Circuits Syst. I Regul. Pap., June, 2025

2023

GRILAPE: Graph Representation Inductive Learning-based Average Power Estimation for Frontend ASIC RTL Designs.

Rakesh M. B., Pabitra Das, Sai Pranav K. R, Amit Acharyya

Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023

2022

GLAAPE: Graph Learning Assisted Average Power Estimation for Gate-level Combinational Designs.

Rakesh M. B., Sai Pranav K. R, Pabitra Das, Amit Acharyya

Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022