Sai Prashanth Mallellu
Orcid: 0009-0002-1271-816X
According to our database1,
Sai Prashanth Mallellu authored at least 3 papers
between 2025 and 2026.
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Bibliography
2026
An FSM-Enabled Reconfigurable Debugging Approach for Area-Optimized FIR Filters on FPGA Platforms.
IET Circuits Devices Syst., 2026
2025
CoRR, January, 2025
FAPL-DM-BC: A Secure and Scalable FL Framework with Adaptive Privacy and Dynamic Masking, Blockchain, and XAI for the IoVs.
CoRR, January, 2025