Sameer Pawanekar

According to our database, Sameer Pawanekar authored at least 8 papers between 2013 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2021

Performance of Reinforcement Learning Simulation: x86 v/s ARM.

Sameer Pawanekar, Geetanjali Udgirkar

Proceedings of the Advances in Computing and Data Sciences - 5th International Conference, 2021

2018

<i>Kapees3</i>: A High-Quality VLSI Placement Tool Using Nesterov's Method for Density Penalty.

Sameer Pawanekar, Kalpesh Kapoor, Gaurav Trivedi

J. Circuits Syst. Comput., 2018

2017

Analytical Partitioning: Improvement over FM.

Sameer Pawanekar, Gaurav Trivedi

Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

Fast FPGA Placement Using Analytical Optimization.

Sameer Pawanekar, Gaurav Trivedi

Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

2015

A Nonlinear Analytical Optimization Method for Standard Cell Placement of VLSI Circuits.

Sameer Pawanekar, Gaurav Trivedi, Kalpesh Kapoor

Proceedings of the 28th International Conference on VLSI Design, 2015

Net weighing based timing driven standard cell placer.

Sameer Pawanekar, Gaurav Trivedi

Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

TSV aware standard cell placement for 3D ICs.

Sameer Pawanekar, Gaurav Trivedi

Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

2013

Kapees: A New Tool for Standard Cell Placement.

Sameer Pawanekar, Kalpesh Kapoor, Gaurav Trivedi

Proceedings of the VLSI Design and Test, 17th International Symposium, 2013