Gaurav Trivedi

According to our database1, Gaurav Trivedi authored at least 36 papers between 2006 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2019
Analysis, Modeling and Optimization of Equal Segment Based Approximate Adders.
IEEE Trans. Computers, 2019

Design and Implementation of Low-Power High-throughput PRNGs for Security Applications.
Proceedings of the 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems, 2019

RiverOpt: A Multiobjective Optimization Framework Based on Modified River Formation Dynamics Heuristic.
Proceedings of the 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems, 2019

Current Collapse Reduction Technique Using N-Doped Buffer Layer into the Bulk Region of a Gate Injection Transistor.
Proceedings of the 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems, 2019

2018
Analysis and Design of Adders for Approximate Computing.
ACM Trans. Embedded Comput. Syst., 2018

Multiobjective analog/RF circuit sizing using an improved brain storm optimization algorithm.
Memetic Computing, 2018

Minimizing area of VLSI power distribution networks using river formation dynamics.
J. Systems and IT, 2018

Kapees3: A High-Quality VLSI Placement Tool Using Nesterov's Method for Density Penalty.
Journal of Circuits, Systems, and Computers, 2018

NLPReViz: an interactive tool for natural language processing on clinical text.
JAMIA, 2018

Accuracy enhancement of equal segment based approximate adders.
IET Computers & Digital Techniques, 2018

PGIREM: Reliability-Constrained IR Drop Minimization and Electromigration Assessment of VLSI Power Grid Networks Using Cooperative Coevolution.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

An Interactive NLP Tool for Signout Note Preparation.
Proceedings of the IEEE International Conference on Healthcare Informatics, 2018

Towards Interactive Natural Language Processing in Clinical Care.
Proceedings of the IEEE International Conference on Healthcare Informatics, 2018

2017
Optimization of 2.4 GHz CMOS Low Noise Amplifier Using Hybrid Particle Swarm Optimization with Lévy Flight.
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

Markov Chain Model Using Lévy Flight for VLSI Power Grid Analysis.
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

FEM Based Device Simulator for High Voltage Devices.
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

Analytical Partitioning: Improvement over FM.
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

Fast FPGA Placement Using Analytical Optimization.
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

Approxhash: delay, power and area optimized approximate hash functions for cryptography applications.
Proceedings of the 10th International Conference on Security of Information and Networks, 2017

2016
A Novel Capacitorless DRAM Cell Design Using Band-Gap Engineered Junctionless Double-Gate FET.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Exploring Approximate Computing for Yield Improvement via Re-design of Adders for Error-Resilient Applications.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Applying River Formation Dynamics to Analyze VLSI Power Grid Networks.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

2015
A Nonlinear Analytical Optimization Method for Standard Cell Placement of VLSI Circuits.
Proceedings of the 28th International Conference on VLSI Design, 2015

A High-Performance Energy-Efficient Hybrid Redundant MAC for Error-Resilient Applications.
Proceedings of the 28th International Conference on VLSI Design, 2015

Variability-aware parametric yield enhancement via post-silicon tuning of hybrid redundant MAC units.
Proceedings of the VLSI Design, Automation and Test, 2015

Net weighing based timing driven standard cell placer.
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

TSV aware standard cell placement for 3D ICs.
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

Parallel two step random walk algorithm to analyze VLSI power grid networks.
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

Applying an Interactive Machine Learning Approach to Statutory Analysis.
Proceedings of the Legal Knowledge and Information Systems, 2015

Clinical Text Analysis Using Interactive Natural Language Processing.
Proceedings of the 20th International Conference on Intelligent User Interfaces Companion, 2015

2013
A Security Framework for NoC Using Authenticated Encryption and Session Keys.
CSSP, 2013

Kapees: A New Tool for Standard Cell Placement.
Proceedings of the VLSI Design and Test, 17th International Symposium, 2013

2007
Application of DC Analyzer to Combinatorial Optimization Problems.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Parallelization of DC Analysis through Multiport Decomposition.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Application of Fast DC Analysis to Partitioning Hypergraphs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
Fast DC Analysis and Its Application to Combinatorial Optimization Problems.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006


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