Sampath Dakshinamurthy

According to our database, Sampath Dakshinamurthy authored at least 2 papers between 2011 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2025

A 0.5pJ/bit 7.2Gbps HBM3 PHY on Intel4 with EMIB Packaging and Unmatched Receiver Architecture on PHY Side with Per Bit Deskew Correction.

Aakash Hasmukhray Mehta, Javed S. Gaggatur, Mohammad M. Rashid, Sampath Dakshinamurthy, Aruna Kumar Lakya Srinivasamurthy, Anil Kumar Goyal, Subbarao Manam, Harshit Gupta, Sandeep Sukumar, Vipin K. Mishra, Koushik N. S, Santosh Nekkanti, Sambaran Mitra, Pooja K. Jadhav, Miryala Chandra Shekar, Dudekula Humayun, Michael C. Rifani, Jianyong Xie, Andrew P. Collins

Proceedings of the 38th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems, 2025

2011

A 32nm Westmere-EX Xeon^® enterprise processor.

Shankar Sawant, Utpal Desai, Gururaj Shamanna, Lokesh Sharma, Mandar Ranade, Anil Agarwal, Sampath Dakshinamurthy, Rajagopal Narayanan

Proceedings of the IEEE International Solid-State Circuits Conference, 2011