Sandeep Garg

According to our database, Sandeep Garg authored at least 4 papers between 2019 and 2020.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2020

A 1-bit full adder using CNFET based dual chirality high speed domino logic.

Sandeep Garg, Tarun Kumar Gupta, Amit Kumar Pandey

Int. J. Circuit Theory Appl., 2020

2019

A New Technique for Designing Low-Power High-Speed Domino Logic Circuits in FinFET Technology.

Sandeep Garg, Tarun Kumar Gupta

J. Circuits Syst. Comput., 2019

FDSTDL: Low-power technique for FinFET domino circuits.

Sandeep Garg, Tarun Kumar Gupta

Int. J. Circuit Theory Appl., 2019

Low leakage domino logic circuit for wide fan-in gates using CNTFET.

Sandeep Garg, Tarun Kumar Gupta

IET Circuits Devices Syst., 2019